This isn't really so mysterious as the article makes it out. There have already been leaks of a new mid-tier platform, for lower-end Granite Rapids & Sierra Forest CPUs, for quite a while. I guess nobody bothered to use google, before writing this.
Intel's next-gen Granite Rapids-SP Xeon CPUs have also been pictured and will be compatible with the LGA 4710 socket.
wccftech.com
If you think about it, it makes sense that not everyone would want a honking-big 12-channel LGA 7529 socket, especially for lower-spec CPU models. So, like AMD's Siena EPYC 8004 series, which launched on their new SP6 socket (LGA 4844), Intel is adding a smaller socket to their lineup.
I just hope they use that smaller socket for Xeon W models, since workstation pricing has gotten so nuts. Not that it really matters for me, as I'm permanently priced out of that segment.
Given that the LGA4710 socket is physically the same as LGA4677, perhaps the main question is why Intel would design a new socket for a new processor form factor aimed at the same applications as existing processors.
Obviously because speeds & feed change, over the years. Sapphire Rapids was originally supposed to be launched in like 2021, by the time that platform was finalized. It's hardly surprising that its socket won't meet some requirements of the CPUs being introduced in 2024.
Not only that, but Intel has a long-standing precedent of using the same socket for 2 generations. The big exception to this was Ice Lake, which (probably due to a generation of Xeons being cancelled) had its own socket.
we purportedly avoided calling products in an LGA4710 form factor a CPU, which is for a reason: Intel sells a boatload of data center and workstation products, so it may use the LGA4710 form factor for a next-generation workstation or special-purpose server system-on-chips, CPUs, FPGAs, or even GPUs.
No, you "purposely" avoided calling it that. And the author should have enough sense to know this isn't for GPUs, which need far more memory bandwidth to use external DRAM and probably have too few other I/Os to justify so many pins. Putting modern FPGAs in such a socket would also be unprecedented, I think.
IMO, this particular author should really know better than to crawl out onto this speculative branch.
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