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It is strange that there are systems out, but Intel has yet to give a presentation of the details of that 408MB of L2 SRAM cache. It appears to be a mfg achievement comparable to the 3d V-cache we see so much publicity about.
 
It is strange that there are systems out, but Intel has yet to give a presentation of the details of that 408MB of L2 SRAM cache. It appears to be a mfg achievement comparable to the 3d V-cache we see so much publicity about.
I mean, when you compare the sheer package footprint of this huge data enter GPU to AMD’s client ~80mm2 CCD chiplet size (X3D cache chiplet in particular only covers on-die L3 and a bit of L2)… they’re both comparatively impressive. This is a packaging tour de force for Intel though, and quite a monumental achievement.

SRAM libraries for cache/tags can be made very dense when not much combinational logic is present.

Edit: I misread “comparable” as “compared”, my mistake lol. Either way, I’m glad these packaging advancements are happening. It’ll be really interesting when truly active-on-active die stacking becomes feasible/mainstream.
 
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