Excellent articles. I enjoyed reading them. I did not know a lot of the nuances of the P4 pipeline or the EV6 bus.
One thing that was mentioned and I had always believed to the contrary, was that CISC (x86) instructions are large. I have always believed that x86 instructions are on the average smaller than other processor instructions (RISC, VLIW, EPIC)
“The problem is that they're big, unwieldy CISC instructions and the K7, like the P6, is basically (gasp!) a RISC CPU”
“…the fact that modern x86 processors like the Athlon, PIII, and P4 need to break down large, complex x86 instructions into smaller, more easily scheduled operations.”
So I looked back at the articles and found a link to this <A HREF="http://www.arstechnica.com/cpu/4q99/risc-cisc/rvc-1.html" target="_new">rvc-1.html</A>.
In which the author Hannibal gives a great evolutionary debate on the aforementioned topic. In the end, I still believe that x86 instructions are smaller than their PPC, MIPS, PA-RISC counterparts and in no way am I saying better. Just cosmetically speaking.
Just my thoughts and reactions
Schmide.
(Links to the other articles <A HREF="http://www.arstechnica.com/cpu/3q99/k7_theory/k7-one-4.html" target="_new">k7-one-4.html</A> and <A HREF="http://arstechnica.com/cpu/01q2/p4andg4e/p4andg4e-1.html" target="_new">p4andg4e-1.html</A> )