So I've been reading the architecture papers on the Ryzen 5000 (Zen 3) architecture.
Question 2: Since the IO die is unchanged (AMD's wording) and the IO Die is responsible for BUS communications, why is Smart Access Memory limited to Ryzen 5000 series when Ryzen 3000 series is PCIe 4.0 compliant? Is this an artificial limitation?
- The IO Die in unchanged.
- Under Zen 2, when a cache miss occurred, it went to the IO Die and then back to the chiplette.
- Zen 3 stays on the chiplette since it has a unified L3 cache.
Question 2: Since the IO die is unchanged (AMD's wording) and the IO Die is responsible for BUS communications, why is Smart Access Memory limited to Ryzen 5000 series when Ryzen 3000 series is PCIe 4.0 compliant? Is this an artificial limitation?