Cells hold an amount of electrons (a charge) which corresponds to different bits depending on the value. There's a limit (threshold) of discernment, which 15nm planar was close to hitting with 3-bit MLC (TLC) - specifically, you had 100 electrons or less with a threshold of about 10, so TLC's 8 voltage states (technically ER and 7 states) was a hard limit. 3D NAND is almost an order-of-magnitude larger effectively, but it can suffer from more disturb because there's more directions where other cells lie; as a result, these types of disturb are based on "X" and "Y" coordinates for example. However, much of this disturb, including read disturb, is basically negligible given the size and distance of the cells. I could go into the technical details but suffice it to say, there are constant advancements to mitigate things like program disturb.
In any case, over time you will have things like leakage which impact retention. The cells also wear down over time from the program/erase cycle. Workload type and temperature can impact this, too. However, in general, modern controllers will keep a log/table of biases for this and adjust the threshold windows accordingly. Eventually you have to rely on ECC and then parity. Nevertheless, improvements are also being made here, as in the manufacturing process itself (since you're just string-stacking decks after a while, although alignment can be an issue). NAND endurance is an issue but obviously we've moved to TLC and soon QLC so it's more of a secondary concern in the consumer market. Consumer drives also have multiple modes, e.g. SLC caching, which can be utilized intelligently to defer writes, esp. with DRAM, in order to reduce wear via write amplification.
2D/planar is inherently different in structure to 3D so shouldn't be directly compared. 2D/planar is in fact still utilized with small density SLC, NOR flash, etc. There's also ultra low latency 3D SLC. Chia retail drives now exist that are QLC in permanent and full SLC/pSLC mode - but people often confuse this for being identical to native SLC. That is NOT the case and is important to realize when comparing QLC and TLC, too; while you can run QLC in TLC mode by just having 3 bits in a cell (e.g. Kioxia's 1.33Tb/die QLC to 1Tb/die TLC), QLC cells on average tend to already be smaller and the circuitry may be different. A good example is that Intel's latest data center (DC) drive is sold as 144L TLC when in reality it's their 144L QLC (floating gate architecture!) in TLC mode. This has interesting results on endurance.
It's rare to go up in layers without other improvements, including endurance, but there's also the question of "is it relevant?" With quality consumer flash and usage, usually not.