Same rules apply for any integrated circuit design. The larger the die area, the less chips per wafer. Less chips per wafer with a given yield percentage means that there is a higher chance of failure on a smaller number of chips. Everything is cost per wafer.
So if you plan for 128 chips on a wafer with a yield of 95% you can write off 7 chips.
121 chips with a wafer cost of $6000, means each of your chips is $50 base cost = $5650
512 chips per wafer, you write off 26 chips, but your chips cost $12.30 each = $5680, an extra $30. Now scale that up to to the millions in product and a small percentage is a huge amount of money.
Smaller the chip, higher the yield, equals more saleable product. And that is at the fab side, at each step you are adding value until you reach the true Bill of Materials for a product, then you can set the sale price for profit, and the ability to be flexible with competition.
That aside, SoC are designed to be power efficient, you don't want a large SoC as that means more internal resistance, and more power draw from all the extra transistors.