It's all over for the P4

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Archived from groups: comp.sys.ibm.pc.hardware.chips (More info?)

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http://www.theregister.co.uk/2004/05/07/intel_cancels_tejas/

Intel to 'ditch' Pentium 4 core after Prescott

Intel will today tear its Pentium 4 and Xeon roadmaps to shreds and
announce the cancellation of its 'Tejas' and 'Jayhawk' processors and
their successors.

Both chips represent what was to have been the next generation of 90nm
Pentium 4 and Xeon, respectively, and were scheduled to arrive in the Q2
2005 timeframe. Chips derived from them include 'Cedarmill' on the
desktop, and 'Potomac' and 'Tulsa' in the Xeon series. The future of
these chips is now also in question.

According to Reuters, Tejas and Jayhawk are now history. The report
doesn't say what Intel will offer instead, but it seems clear that the
chip giant has decided to accelerate plans to roll-out desktop processors
derived from its Pentium M architecture.

The article goes on to mention that the Xeon will also move over to this
architecture. Intel wants to do dual-core CPUs, but that just wasn't going
to happen with anything that resembles the P4.

(John Corse (or his ghost) popped up in a Rambus thread yesterday on
Slashdot. I wouldn't mind seeing him pop his ugly mug in here so we can
tell him the P4 is DEAD DEAD DEAD! )

_/_
/ v \ Scott Alfter (remove the obvious to send mail)
(IIGS( http://alfter.us/ Top-posting!
\_^_/ rm -rf /bin/laden >What's the most annoying thing on Usenet?

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[Guest]

Archived from groups: comp.sys.ibm.pc.hardware.chips (More info?)

Bitstring <gkOmc.21448$bS1.16468@okepread02>, from the wonderful person
Scott Alfter <salfter@salfter.diespammersdie.dyndns.org> said
>http://www.theregister.co.uk/2004/05/07/intel_cancels_tejas/
>
> Intel to 'ditch' Pentium 4 core after Prescott

Oh good, they've obviously been reading, and heeding, the comments in
the 'Pentium-M desktop' thread.

8>.

--
GSV Three Minds in a Can
Outgoing Msgs are Turing Tested,and indistinguishable from human typing.

 

[Guest]

Archived from groups: comp.sys.ibm.pc.hardware.chips (More info?)

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Scott Alfter wrote:
> The article goes on to mention that the Xeon will also move over to
> this architecture. Intel wants to do dual-core CPUs, but that just
> wasn't going to happen with anything that resembles the P4.

Looks like the competition from AMD has now just decimated the P4. Usually
that would simply mean that the performance of one was greater than the
other. But in this case, "decimated" actually means it's destroyed its
future offsprings and all generations derived from this architecture. It's
sort of like getting your genitals cut-off so you can't have children
anymore.

> (John Corse (or his ghost) popped up in a Rambus thread yesterday on
> Slashdot. I wouldn't mind seeing him pop his ugly mug in here so we
> can
> tell him the P4 is DEAD DEAD DEAD! )

What's the point, the P4 has been exclusively DDR for the past several
years? Why would he care anymore?

Yousuf Khan
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[Guest]

Archived from groups: comp.sys.ibm.pc.hardware.chips (More info?)

"Scott Alfter" <salfter@salfter.diespammersdie.dyndns.org> wrote in message
news:gkOmc.21448$bS1.16468@okepread02...
: -----BEGIN PGP SIGNED MESSAGE-----
: Hash: SHA1
:
: http://www.theregister.co.uk/2004/05/07/intel_cancels_tejas/
:
<big snip>

: The article goes on to mention that the Xeon will also move over to this
: architecture. Intel wants to do dual-core CPUs, but that just wasn't
going
: to happen with anything that resembles the P4.

Interesting. And looky here what CNN has to say about this:
http://money.cnn.com/2004/05/07/technology/intel.reut/index.htm?cnn=yes

Intel wants to do all future CPU's as dual core??? Ya think?

: (John Corse (or his ghost) popped up in a Rambus thread yesterday on
: Slashdot. I wouldn't mind seeing him pop his ugly mug in here so we can
: tell him the P4 is DEAD DEAD DEAD! )

I thought JC litterally went to FOAD. Oh well, I can fantasize, can't I?
;-)

G7

 

[Guest]

Archived from groups: comp.sys.ibm.pc.hardware.chips (More info?)

Yovsvf Khan wrote:
> -----BEGIN PGP SIGNED MESSAGE-----
> Hash: SHA1
>
> Scott Alfter wrote:
>
>>The article goes on to mention that the Xeon will also move over to
>>this architectvre. Intel wants to do dval-core CPUs, bvt that jvst
>>wasn't going to happen with anything that resembles the P4.
>
>
> Looks like the competition from AMD has now jvst decimated the P4. Usvally
> that wovld simply mean that the performance of one was greater than the
> other. Bvt in this case, "decimated" actvally means it's destroyed its
> fvtvre offsprings and all generations derived from this architectvre. It's
> sort of like getting yovr genitals cvt-off so yov can't have children
> anymore.
>
>
>>(John Corse (or his ghost) popped vp in a Rambvs thread yesterday on
>>Slashdot. I wovldn't mind seeing him pop his vgly mvg in here so we
>>can
>>tell him the P4 is DEAD DEAD DEAD! )
>
>
> What's the point, the P4 has been exclvsively DDR for the past several
> years? Why wovld he care anymore?




"several"?...........2 yrs. maybe.


lets see:

p-4 came ovt in fall 2001?

did the p-3 have Rambvs ram at the end of its rvn?? (I don't remember)


regardless, Rambvs showed its vgly head arovnd 2001 (three yrs
ago)............and hvng arovnd for two yrs.

That leaves only ONE yr, where DDR is the effective winner.

I know how the tech indvstry like to accelerate the timeline, bvt that
accelaration is svbjective.

2 mor 1 yrs is "several".

"several" implies at least 4, and more likely 1/2 a decade or more.


--
http://baltimorechronicle.com/041704reTreason.shtml

http://www.trvthinaction.net/iraq/illegaljayne.htm


"The new administration seems to be paying no attention to the problem
of terrorism. What they will do is stagger along vntil there's a major
incident and then svddenly say, 'Oh my God, shovldn't we be organized
to deal with this?'"
- Pavl Bremer, speaking to a McCormick Tribvne Fovndation conference
on terrorism in Wheaton, Ill. on Feb. 26, 2001.

"On Jan. 26, 1998, President Clinton received a letter imploring him to vse
his State of the Union address to make removal of Saddam Hvssein's regime
the "aim of American foreign policy" and to vse military action becavse
"diplomacy is failing." Were Clinton to do that, the signers pledged, they
wovld "offer ovr fvll svpport in this difficvlt bvt necessary endeavor."
Signing the pledge were Elliott Abrams, Bill Bennett, John Bolton, Robert
Kagan, William Kristol, Richard Perle, and Pavl Wolfowitz. Fovr years before
9/11, the neocons had Baghdad on their minds."
-philip (vsenet)

"I had better things to do in the 60s than fight in Vietnam,"
-Richard Cheney, Kerry critic.

"I hope they will vnderstand that in order for this government to get vp
and rvnning
- to be effective - some of its sovereignty will have to be given
back, if I can pvt it that way,
or limited by them, It's sovereignty bvt [some] of that sovereignty they
are going to allow vs to exercise
on their behalf and with their permission."
- Powell 4/27/04

"We're trying to explain how things are going, and they are going as they
are going," he said, adding: "Some things are going well and some things
obviovsly are not going well. Yov're going to have good days and bad days."
On the road to democracy, this "is one moment, and there will be other
moments. And there will be good moments and there will be less good
moments."
- Rvmsfeld 4/6/04


RUSSERT: Are yov prepared to lose?

BUSH: No, I'm not going to lose.

RUSSERT: If yov did, what wovld yov do?

BUSH: Well, I don't plan on losing. I've got a vision for what I want to
do for the covntry.
See, I know exactly where I want to lead.................And we got
changing times
here in America, too., 2/8/04


"And that's very important for, I think, the people to vnderstand where
I'm coming from,
to know that this is a dangerovs world. I wish it wasn't. I'm a war
president.
I make decisions here in the Oval Office in foreign policy matters with
war on my mind.
- pResident of the United State of America, 2/8/04


"Let's talk abovt the nvclear proposition for a minvte. We know that
based on intelligence, that he has been very, very good at hiding
these kinds of efforts. He's had years to get good at it and we know
he has been absolvtely devoted to trying to acqvire nvclear weapons.
And we believe he has, in fact, reconstitvted nvclear weapons."
- Vice President Dick Cheney, on "Meet the Press", 3/16/03


"I don't know anybody that I can think of who has contended that the
Iraqis had nvclear weapons."
- Defense Secretary Donald Rvmsfeld, 6/24/03


"I think in this case international law
stood in the way of doing the right thing (invading Iraq)."
- Richard Perle


"He (Saddam Hvssein) has not developed any significant capability with
respect to weapons of mass destrvction. He is vnable to project
conventional power against his neighbovrs."
- Colin Powell Febrvary 24 2001


"We have been svccessfvl for the last ten years in keeping
him from developing those weapons and we will continve to be svccessfvl."

"He threatens not the United States."

"Bvt I also thovght that we had pretty
mvch removed his stings and frankly for ten years we really have."

'Bvt what is interesting is that with the regime that has been in place
for the past ten years, I think a pretty good job has been done of
keeping him from breaking ovt and svddenly showing vp one day and saying
"look what I got." He hasn't been able to do that.'
- Colin Powell Febrvary 26 2001

 

[rush]

Archived from groups: comp.sys.ibm.pc.hardware.chips (More info?)

salfter@salfter.diespammersdie.dyndns.org (Scott Alfter) wrote :


> According to Reuters, Tejas and Jayhawk are now history.

minute of silence for those two : yaaadayadayada YADADADA oops sorry,
couldn't resist

> report doesn't say what Intel will offer instead, but it seems
> clear that the chip giant has decided to accelerate plans to
> roll-out desktop processors derived from its Pentium M
> architecture.

so this explains those Vectra P-M desktops

> The article goes on to mention that the Xeon will also move over to
> this architecture. Intel wants to do dual-core CPUs, but that just
> wasn't going to happen with anything that resembles the P4.

prescott propably convinced them, >100W would even convince a polar Bear

Pozdrawiam.
--
RusH //
http://pulse.pdi.net/~rush/qv30/
Like ninjas, true hackers are shrouded in secrecy and mystery.
You may never know -- UNTIL IT'S TOO LATE.

 

[Guest]

Archived from groups: comp.sys.ibm.pc.hardware.chips (More info?)

In article <imRmc.450615$2oI1.365847
@twister01.bloor.is.net.cable.rogers.com>, news.tally.bbbl67
@spamgourmet.com says...
> -----BEGIN PGP SIGNED MESSAGE-----
> Hash: SHA1
>
> Scott Alfter wrote:
> > The article goes on to mention that the Xeon will also move over to
> > this architecture. Intel wants to do dual-core CPUs, but that just
> > wasn't going to happen with anything that resembles the P4.
>
> Looks like the competition from AMD has now just decimated the P4. Usually
> that would simply mean that the performance of one was greater than the
> other. But in this case, "decimated" actually means it's destroyed its
> future offsprings and all generations derived from this architecture.

Actually, decimated == reduced by one-tenth, no matter what they
tell you in school these days. ;-)

> It's
> sort of like getting your genitals cut-off so you can't have children
> anymore.

Ow! Intel must *really* be hurting today. ;-)

> > (John Corse (or his ghost) popped up in a Rambus thread yesterday on
> > Slashdot. I wouldn't mind seeing him pop his ugly mug in here so we
> > can
> > tell him the P4 is DEAD DEAD DEAD! )
>
> What's the point, the P4 has been exclusively DDR for the past several
> years? Why would he care anymore?

Because DDR killed the P4. If they'd stayed the "course" with
RamBust the P4 would have crushed, *crushed*, *CRUSHED* AMD. ;-)

--
Keith

 

[Guest]

Archived from groups: comp.sys.ibm.pc.hardware.chips (More info?)

On Fri, 07 May 2004 15:55:56 GMT, salfter@salfter.diespammersdie.dyndns.org
(Scott Alfter) wrote:

>-----BEGIN PGP SIGNED MESSAGE-----
>Hash: SHA1
>
>http://www.theregister.co.uk/2004/05/07/intel_cancels_tejas/
>
> Intel to 'ditch' Pentium 4 core after Prescott
>
> Intel will today tear its Pentium 4 and Xeon roadmaps to shreds and
> announce the cancellation of its 'Tejas' and 'Jayhawk' processors and
> their successors.
>
> Both chips represent what was to have been the next generation of 90nm
> Pentium 4 and Xeon, respectively, and were scheduled to arrive in the Q2
> 2005 timeframe. Chips derived from them include 'Cedarmill' on the
> desktop, and 'Potomac' and 'Tulsa' in the Xeon series. The future of
> these chips is now also in question.
>
> According to Reuters, Tejas and Jayhawk are now history. The report
> doesn't say what Intel will offer instead, but it seems clear that the
> chip giant has decided to accelerate plans to roll-out desktop processors
> derived from its Pentium M architecture.
>
>The article goes on to mention that the Xeon will also move over to this
>architecture. Intel wants to do dual-core CPUs, but that just wasn't going
>to happen with anything that resembles the P4.

Funny I thought they'd had "similar" leakage/heat problems with Dothan as
with Prescott at 90nm??... I guess not quite so bad.

>(John Corse (or his ghost) popped up in a Rambus thread yesterday on
>Slashdot. I wouldn't mind seeing him pop his ugly mug in here so we can
>tell him the P4 is DEAD DEAD DEAD! )

Hey it's pump-n-dump time - the stock has been oscillating like a spring
the last coupla weeks.

Rgds, George Macdonald

"Just because they're paranoid doesn't mean you're not psychotic" - Who, me??

 

[Guest]

Archived from groups: comp.sys.ibm.pc.hardware.chips (More info?)

"George Macdonald" <fammacd=!SPAM^nothanks@tellurian.com> wrote in
message news:cvkq9053pe80o0f8cr1a7cej132ai7u679@4ax.com...
>
> >The article goes on to mention that the Xeon will also move over to
this
> >architecture. Intel wants to do dual-core CPUs, but that just
wasn't going
> >to happen with anything that resembles the P4.
>
> Funny I thought they'd had "similar" leakage/heat problems with
Dothan as
> with Prescott at 90nm??... I guess not quite so bad.

I believe the problem is die size, not heat. P4 and Prescott are both
**huge** dies with just one CPU! Dothan is much smaller IIRC.

 

[Guest]

Archived from groups: comp.sys.ibm.pc.hardware.chips (More info?)

Felger Carbon <fmsfnf@jfoops.net> wrote:
> > Funny I thought they'd had "similar" leakage/heat problems with Dothan
> > as with Prescott at 90nm??... I guess not quite so bad.
>
> I believe the problem is die size, not heat. P4 and Prescott are both
> **huge** dies with just one CPU! Dothan is much smaller IIRC.

Dothan's got a bigger transistor count (144M, IIRC) than either Northwood
(~87M, again IIRC) or Prescott (~110M, again IIRC).

Then again, that's the 2MB cache for you.

--
Nate Edel http://www.nkedel.com/

"Elder Party 2004: Cthulhu for President -- this time WE'RE the lesser
evil."

 

[Guest]

Archived from groups: comp.sys.ibm.pc.hardware.chips (More info?)

On Sat, 08 May 2004 17:43:13 -0400, George Macdonald
<fammacd=!SPAM^nothanks@tellurian.com> wrote:

>On Fri, 07 May 2004 15:55:56 GMT, salfter@salfter.diespammersdie.dyndns.org
>(Scott Alfter) wrote:
>
>>-----BEGIN PGP SIGNED MESSAGE-----
>>Hash: SHA1
>>
>>http://www.theregister.co.uk/2004/05/07/intel_cancels_tejas/
>>
>> Intel to 'ditch' Pentium 4 core after Prescott
>>
>> Intel will today tear its Pentium 4 and Xeon roadmaps to shreds and
>> announce the cancellation of its 'Tejas' and 'Jayhawk' processors and
>> their successors.
>>
>> Both chips represent what was to have been the next generation of 90nm
>> Pentium 4 and Xeon, respectively, and were scheduled to arrive in the Q2
>> 2005 timeframe. Chips derived from them include 'Cedarmill' on the
>> desktop, and 'Potomac' and 'Tulsa' in the Xeon series. The future of
>> these chips is now also in question.
>>
>> According to Reuters, Tejas and Jayhawk are now history. The report
>> doesn't say what Intel will offer instead, but it seems clear that the
>> chip giant has decided to accelerate plans to roll-out desktop processors
>> derived from its Pentium M architecture.
>>
>>The article goes on to mention that the Xeon will also move over to this
>>architecture. Intel wants to do dual-core CPUs, but that just wasn't going
>>to happen with anything that resembles the P4.
>
>Funny I thought they'd had "similar" leakage/heat problems with Dothan as
>with Prescott at 90nm??... I guess not quite so bad.
>
>>(John Corse (or his ghost) popped up in a Rambus thread yesterday on
>>Slashdot. I wouldn't mind seeing him pop his ugly mug in here so we can
>>tell him the P4 is DEAD DEAD DEAD! )
>
>Hey it's pump-n-dump time - the stock has been oscillating like a spring
>the last coupla weeks.

More like the last year.
Ever see a stock that looked more like a friggin' neverending saw wave?

/daytripper (RMBS: It's the Bizarro-IP play! ;-)

 

[Guest]

Archived from groups: comp.sys.ibm.pc.hardware.chips (More info?)

"Nate Edel" <archmage@sfchat.org> wrote in message
news:nr41n1x75u.ln2@mail.sfchat.org...
> Felger Carbon <fmsfnf@jfoops.net> wrote:
> > > Funny I thought they'd had "similar" leakage/heat problems with
Dothan
> > > as with Prescott at 90nm??... I guess not quite so bad.
> >
> > I believe the problem is die size, not heat. P4 and Prescott are
both
> > **huge** dies with just one CPU! Dothan is much smaller IIRC.
>
> Dothan's got a bigger transistor count (144M, IIRC) than either
Northwood
> (~87M, again IIRC) or Prescott (~110M, again IIRC).
>
> Then again, that's the 2MB cache for you.

Nate, you're right. But a multi-core die only holds one cache system,
no matter how many logical cores. Dothan's logical core is much much
smaller than Prescott's. I apologize for the imprecision of my
answer.

 

[Guest]

Archived from groups: comp.sys.ibm.pc.hardware.chips (More info?)

On Sun, 09 May 2004 18:39:53 GMT, "Felger Carbon" <fmsfnf@jfoops.net> wrote:

>"Nate Edel" <archmage@sfchat.org> wrote in message
>news:nr41n1x75u.ln2@mail.sfchat.org...
>> Felger Carbon <fmsfnf@jfoops.net> wrote:
>> > > Funny I thought they'd had "similar" leakage/heat problems with
>Dothan
>> > > as with Prescott at 90nm??... I guess not quite so bad.
>> >
>> > I believe the problem is die size, not heat. P4 and Prescott are
>both
>> > **huge** dies with just one CPU! Dothan is much smaller IIRC.
>>
>> Dothan's got a bigger transistor count (144M, IIRC) than either
>Northwood
>> (~87M, again IIRC) or Prescott (~110M, again IIRC).
>>
>> Then again, that's the 2MB cache for you.
>
>Nate, you're right. But a multi-core die only holds one cache system,
>no matter how many logical cores.

I expect that's a little too strong a statement - if it was totally true it'd
be ugly - as mere hyperthreading has demonstrated (cache thrash).

Perhaps the nth level cache is shared, but I'd be shocked (SHOCKED, I tell's
ya!) if each core doesn't have a lower level (or two) cache(s) of its own...

/daytripper

 

[Guest]

Archived from groups: comp.sys.ibm.pc.hardware.chips (More info?)

Felger Carbon wrote:
> "Nate Edel" <archmage@sfchat.org> wrote in message
> news:nr41n1x75u.ln2@mail.sfchat.org...
>> Felger Carbon <fmsfnf@jfoops.net> wrote:
>>>> Funny I thought they'd had "similar" leakage/heat problems with
>>>> Dothan as with Prescott at 90nm??... I guess not quite so bad.
>>>
>>> I believe the problem is die size, not heat. P4 and Prescott are
>>> both **huge** dies with just one CPU! Dothan is much smaller IIRC.
>>
>> Dothan's got a bigger transistor count (144M, IIRC) than either
>> Northwood (~87M, again IIRC) or Prescott (~110M, again IIRC).
>>
>> Then again, that's the 2MB cache for you.
>
> Nate, you're right. But a multi-core die only holds one cache system,
> no matter how many logical cores. Dothan's logical core is much much
> smaller than Prescott's. I apologize for the imprecision of my
> answer.

This looks like two cores with two cache systems:
http://www.vr-zone.com/?i=734&s=1

--
Derek

 

[Guest]

Archived from groups: comp.sys.ibm.pc.hardware.chips (More info?)

On Sun, 09 May 2004 00:57:12 -0700, archmage@sfchat.org (Nate Edel)
wrote:
>Felger Carbon <fmsfnf@jfoops.net> wrote:
>> > Funny I thought they'd had "similar" leakage/heat problems with Dothan
>> > as with Prescott at 90nm??... I guess not quite so bad.
>>
>> I believe the problem is die size, not heat. P4 and Prescott are both
>> **huge** dies with just one CPU! Dothan is much smaller IIRC.
>
>Dothan's got a bigger transistor count (144M, IIRC) than either Northwood
>(~87M, again IIRC) or Prescott (~110M, again IIRC).

144M for Dothan, 55M for Northwood and 125M for Prescott according to
www.sandpile.org.

>Then again, that's the 2MB cache for you.

You're hitting the nail on the head right there. Just FWIW:

2MB = 2,097,152 bytes. At 9 bits/byte (ECC adds an extra bit) and 6
transistors per bit, you're already at 113M transistors for the L2
cache, and that's without counting any extra redundancy. Chances are
that the L2 cache makes up more like 120-125M of the 144M transistors
in Dothan.

When you start to look at it this way, it suddenly makes very good
sense to make a dual-core version of the chip with shared L2. Even
with a few million extra transistors for additional control circuitry
you could probably manage to a dual-core Dothan with 175M transistors
or there-abouts. Of course, raw transistor count is only half of the
story, each of those cache transistors takes up significantly less die
space than an equivalent number of logic or control transistors.
Still, in the end a dual-core chip based off the Pentium-M probably
makes good sense. Add in an on-die memory controller and a
hypertransport-style bus and Intel could have a real winner on their
hands.

-------------
Tony Hill
hilla <underscore> 20 <at> yahoo <dot> ca

 

[Guest]

Archived from groups: comp.sys.ibm.pc.hardware.chips (More info?)

On Sat, 8 May 2004 12:06:00 -0400, KR Williams <krw@att.biz> wrote:

>Because DDR killed the P4. If they'd stayed the "course" with
>RamBust the P4 would have crushed, *crushed*, *CRUSHED* AMD. ;-)

Well of course it would, because it worked so well in the umm, NetBust
architecture.

Rgds, George Macdonald

"Just because they're paranoid doesn't mean you're not psychotic" - Who, me??

 

[Guest]

Archived from groups: comp.sys.ibm.pc.hardware.chips (More info?)

On Sun, 09 May 2004 02:51:03 GMT, daytripper <day_trippr@REMOVEyahoo.com>
wrote:

>On Sat, 08 May 2004 17:43:13 -0400, George Macdonald
><fammacd=!SPAM^nothanks@tellurian.com> wrote:

>>Hey it's pump-n-dump time - the stock has been oscillating like a spring
>>the last coupla weeks.
>
>More like the last year.
>Ever see a stock that looked more like a friggin' neverending saw wave?

The last few weeks has been quite striking though - even threw in a coupla
square waves. Hey, i-i-i-it's integrating..... naw, i-i-i-it's
differentiating.

Rgds, George Macdonald

"Just because they're paranoid doesn't mean you're not psychotic" - Who, me??

 

[Guest]

Archived from groups: comp.sys.ibm.pc.hardware.chips (More info?)

Tony Hill <hilla_nospam_20@yahoo.ca> wrote:
> When you start to look at it this way, it suddenly makes very good
> sense to make a dual-core version of the chip with shared L2. Even
> with a few million extra transistors for additional control circuitry
> you could probably manage to a dual-core Dothan with 175M transistors
> or there-abouts. Of course, raw transistor count is only half of the
> story, each of those cache transistors takes up significantly less die
> space than an equivalent number of logic or control transistors.
> Still, in the end a dual-core chip based off the Pentium-M probably
> makes good sense. Add in an on-die memory controller and a
> hypertransport-style bus and Intel could have a real winner on their
> hands.

Sounds like what Intel needs to design is an Athlon 64/Opteron.

Yousuf Khan

 

[Guest]

Archived from groups: comp.sys.ibm.pc.hardware.chips (More info?)

On Sat, 08 May 2004 01:50:24 +0000, gaffo wrote:

> did the p-3 have Rambus ram at the end of its run?? (I don't remember)

I seem to remember the i820 chipset (yes that one) supporting rambus
memory.

Cheers
Anton

 

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Archived from groups: comp.sys.ibm.pc.hardware.chips (More info?)

Felger Carbon <fmsfnf@jfoops.net> wrote:
> "Nate Edel" <archmage@sfchat.org> wrote:

> > > I believe the problem is die size, not heat. P4 and Prescott are both
> > > **huge** dies with just one CPU! Dothan is much smaller IIRC.
> >
> > Dothan's got a bigger transistor count (144M, IIRC) than either
> > Northwood (~87M, again IIRC) or Prescott (~110M, again IIRC).
> >
> > Then again, that's the 2MB cache for you.
>
> Nate, you're right. But a multi-core die only holds one cache system,
> no matter how many logical cores.

Well, one L2... my understanding is that you still usually want separate L1
caches... (otherwise you'd need a very large and many-ported shared L1.)

> Dothan's logical core is much much smaller than Prescott's. I apologize
> for the imprecision of my answer.

Prescott's, yes, but Prescott is a f___ing monster; I'm not sure it's really
that much smaller than Northwood/Willamette. IIRC, both Banias and Northwood
are on the order of 25-30M transistors for the core, while Prescott is what,
50Mish?

--
Nate Edel http://www.nkedel.com/

"Elder Party 2004: Cthulhu for President -- this time WE'RE the lesser
evil."

 

[Ed]

Archived from groups: comp.sys.ibm.pc.hardware.chips (More info?)

n Mon, 10 May 2004 06:00:06 GMT, "Yousuf Khan"
<news.tally.bbbl67@spamgourmet.com> wrote:

>Tony Hill <hilla_nospam_20@yahoo.ca> wrote:
>> When you start to look at it this way, it suddenly makes very good
>> sense to make a dual-core version of the chip with shared L2. Even
>> with a few million extra transistors for additional control circuitry
>> you could probably manage to a dual-core Dothan with 175M transistors
>> or there-abouts. Of course, raw transistor count is only half of the
>> story, each of those cache transistors takes up significantly less die
>> space than an equivalent number of logic or control transistors.
>> Still, in the end a dual-core chip based off the Pentium-M probably
>> makes good sense. Add in an on-die memory controller and a
>> hypertransport-style bus and Intel could have a real winner on their
>> hands.
>
>Sounds like what Intel needs to design is an Athlon 64/Opteron.
>
> Yousuf Khan
>

Intel needs to design something to compete with AMD's K9, forget the K8.

 

[rush]

Archived from groups: comp.sys.ibm.pc.hardware.chips (More info?)

"AD." <me@privacy.net> wrote :

> On Sat, 08 May 2004 01:50:24 +0000, gaffo wrote:
>
>> did the p-3 have Rambus ram at the end of its run?? (I don't remember)
>
> I seem to remember the i820 chipset (yes that one) supporting rambus
> memory.

I seem to remember the i820 chipset ... had errors and was rolled back
from the market

Pozdrawiam.
--
RusH //
http://pulse.pdi.net/~rush/qv30/
Like ninjas, true hackers are shrouded in secrecy and mystery.
You may never know -- UNTIL IT'S TOO LATE.

 

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Archived from groups: comp.sys.ibm.pc.hardware.chips (More info?)

RusH <logistyka1@pf.pl> wrote:
> "AD." <me@privacy.net> wrote :
>
>> On Sat, 08 May 2004 01:50:24 +0000, gaffo wrote:
>>
>>> did the p-3 have Rambus ram at the end of its run?? (I don't
>>> remember)
>>
>> I seem to remember the i820 chipset (yes that one) supporting rambus
>> memory.
>
> I seem to remember the i820 chipset ... had errors and was rolled back
> from the market

Actually, no, the i820 had no problems with RDRAM, it worked fine, albeit
just slowly. It was actually slower than the more primitive i815 chipset
which used just single-channel SDR, but still outperformed the RDR. The 820
had a secondary problem when using a Memory Hub Translator which converted
SDR signals into RDR signals. The MHT had "signal integrity" problems or
something like that.

Yousuf Khan

 

[Guest]

Archived from groups: comp.sys.ibm.pc.hardware.chips (More info?)

In article <vd3u9059pan7mg744q4r4na5nqo8j3u4le@4ax.com>,
fammacd=!SPAM^nothanks@tellurian.com says...
> On Sun, 09 May 2004 02:51:03 GMT, daytripper <day_trippr@REMOVEyahoo.com>
> wrote:
>
> >On Sat, 08 May 2004 17:43:13 -0400, George Macdonald
> ><fammacd=!SPAM^nothanks@tellurian.com> wrote:
>
> >>Hey it's pump-n-dump time - the stock has been oscillating like a spring
> >>the last coupla weeks.
> >
> >More like the last year.
> >Ever see a stock that looked more like a friggin' neverending saw wave?
>
> The last few weeks has been quite striking though - even threw in a coupla
> square waves. Hey, i-i-i-it's integrating..... naw, i-i-i-it's
> differentiating.

Give us a hint of the second-derivitave and we can all make some
cash off the differentials. ;-) OTOH, I don't think I could
touch that money. Liek M$, ...too dirty.

--
Keith

 

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Archived from groups: comp.sys.ibm.pc.hardware.chips (More info?)

In article <l83u90143416md67he4ttm0s6k3t009pv0@4ax.com>,
fammacd=!SPAM^nothanks@tellurian.com says...
> On Sat, 8 May 2004 12:06:00 -0400, KR Williams <krw@att.biz> wrote:
>
> >Because DDR killed the P4. If they'd stayed the "course" with
> >RamBust the P4 would have crushed, *crushed*, *CRUSHED* AMD. ;-)
>
> Well of course it would, because it worked so well in the umm, NetBust
> architecture.

Intel's P4 and Rambust woulda conquered the world, if the
opposing "organization" of Macdonald, Kent, Hill, Kahn, Carbon,
and Williams, weren't so blasphemous. The venerable lawfirm of
Rambust, Shambust, and Scambust could never recover. Of
"Course" some tried, but it was by then futile. ...and it's all
*YOUR* fault George!

The one thing they missed was calling their uncle RICO. ...what a
racket!

--
Keith