News Japanese scientists develop simplified EUV scanner that can make production of chips considerably cheaper

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Reading the paper, this comes with a few heavy caveats:
- only 0.2 NA, with a 0.3 NA version being proposed but requires a curved surface photomask to be fabricated (not a trivial task). High-NA EUV is 0.5 NA, and 'standard' EUV is 0.33 NA.
- 10m x 26mm field size. Even the 'small' field of TSMV's high-NA EUV machines is 16.5x26, and 'standard' EUV is 33x26mm.
- all-aspheric optics
- has not been tested in a physical system

So the technique is both lower resolution than both standard and high-NA EUV, a much smaller reticule size than even high-NA EUV, and may require custom 2D curved masks and pellicles requiring new fabrication techniques compared to existing masks and pellicles (as if EUV pellicles weren't already enough of an issue).. It also requires fabrication of perforated aspheric Bragg mirrors, which is nontrivial.
 
So should ASML be worried as we enter the Angstrom era, or is this tech not for 18A, 14A and below, but rather, 3nm, 4nm ?
Well, using the Rayleigh criterion equation, CD = k1 * λ / NA, even if they do achieve a k1 factor of 0.25 (which is the physical limit) and an EUV wavelength of 13.5nm, they would achieve a critical dimension of 16.875nm if they achieve 0.2NA and 11.25nm if they achieve 0.3NA.
 
Well, using the Rayleigh criterion equation, CD = k1 * λ / NA, even if they do achieve a k1 factor of 0.25 (which is the physical limit) and an EUV wavelength of 13.5nm, they would achieve a critical dimension of 16.875nm if they achieve 0.2NA and 11.25nm if they achieve 0.3NA.
I mean manufacturing node. Is it 3nm class or sub 2nm class?
 
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