While browsing around AMD's site for some information I ran across <A HREF="http://www.amd.com/us-en/assets/content_type/white_papers_and_tech_docs/25759.pdf" target="_new">this PDF file</A> that lists 'Errata'. Let me list a few of the items detailed:
Don't shoot the messenger. This is all straight out of AMD's documentation. If you own an Opteron or Athlon 64 I would highly suggest that you look up what bugs you are potentially affected by and see about trying to implement any of AMD's suggested workarounds. Better safe than sorry.
<A HREF="http://ars.userfriendly.org/cartoons/?id=20031017" target="_new">Then what's your poison of choice?
Soymilk. I was raised on the stuff.
Ah. What's it made of?
Soy.
Is that soy as in soylent green?</A>
<font color=green><b>60 Single Machine Check Error May Report Overflow</b>
<b>Description</b>
A single parity error encountered in the data cache tag array may incorrectly report the detection of
multiple errors, as indicated by the overflow bit of the DC Machine Check Status register (bit 62 of
MSR 0x401).
<b>Potential Effect on System</b>
System software may be informed of a machine check overflow when only a single error was actually
encountered.</font color=green>
<font color=green><b>62 Task Gates With Breakpoints Enabled May Cause Unexpected Faults</b>
<b>Description</b>
When a task gate is used by a CALL or JMP instruction and any debug breakpoint is enabled through
the DR7.LE or GE bits, the processor may incorrectly use the new TSS base [15:0] contained in the
new TSS as a selector. This will most likely lead to a GP fault with an error code of the new TSS base.
<b>Potential Effect on System</b>
Unexpected faults leading to unpredictable system failure.</font color=green>
<font color=green><b>63 TLB Flush Filter Causes Coherency Problem in Multiprocessor Systems</b>
<b>Description</b>
If the TLB flush filter is enabled in a multiprocessor configuration, coherency problems may arise
between the page tables in memory and the translations stored in the on-chip TLBs. This can result in
the possible use of stale translations even after software has performed a TLB flush.
<b>Potential Effect on System</b>
Unpredictable system failure.</font color=green>
<font color=green><b>66 Upstream Read Response Delayed by Downstream Posted Writes</b>
<b>Description</b>
An upstream read to main memory can be delayed when the following sequence occurs:
1. The processor issues one or more posted writes downstream.
2. The processor evicts a line from its cache.
3. The chipset performs an upstream read to memory with the PassPW bit set in the HyperTransport
packet.
In this case, the read should pass the downstream posted writes but due to a resource conflict in the
internal request queues, the read is delayed until the processor’s cache line is written and all
previously enqueued posted writes have completed.
<b>Potential Effect on System</b>
Unexpectedly large latencies may be experienced during upstream memory reads, potentially
resulting in performance anomolies or functional failures, depending on the buffering capabilities of
external devices.</font color=green>
<font color=green><b>69 Multiprocessor Coherency Problem with Hardware Prefetch Mechanism</b>
<b>Description</b>
If the on-chip hardware prefetch mechansim generates a prefetch with write intent for a cache line
that is also found to be present in the instruction cache, then the eventual prefetch response from the
system is incorrectly discarded by the processor.
In the event the prefetched line was transferred in the modified state from another processor’s cache,
that processor’s modified data is lost.
<b>Potential Effect on System</b>
Multiprocessor memory coherency issues leading to unpredictable system failure.</font color=green>
<font color=green><b>74 Registered DIMM Exit-Self-Refresh Requirements Not Met</b>
<b>Description</b>
When sequencing registered DIMMs out of self refresh state at the completion of an S1, S3 or
LDTSTOP_L initiated HyperTransport link width/frequency change, certain sequencing
requirements of the registered DIMMs are not met.
<b>Potential Effect on System</b>
Memory system failure leading to unpredictable system failure.</font color=green>
<font color=green><b>80 Registered DIMM Initialization Requirements Not Met</b>
<b>Description</b>
When initializing registered DIMMs after a powerup or warm reset assertion, the time interval
between the deassertion of MEMRESET_L and the assertion of CKE is not sufficient for some
DIMMs.
<b>Potential Effect on System</b>
The memory system may fail to initialize, leading to boot failure.</font color=green>
<font color=green><b>86 DRAM Data Masking Feature Can Cause ECC Failures</b>
<b>Description</b>
Under certain conditions, the memory controller fails to generate a DRAM read request when
performing partial writes to an already allocated write combining buffer. Because the DRAM is not
read for these subsequent write requests, the generated ECC bits are incorrect.
<b>Potential Effect on System</b>
Incorrect data can be read back from DRAM.</font color=green>
<font color=green><b>89 Potential Deadlock With Locked Transactions</b>
<b>Description</b>
Downstream non-posted requests to devices that are dependent on the completion of an upstream
non-posted request can cause a deadlock in the presence of transactions resulting in bus locks, as
shown in the following two scenarios:
1. A downstream non-posted read to the LPC bus occurs while an LPC bus DMA is in progress. The
legacy LPC DMA blocks downstream traffic until it completes its upstream reads.
2. A downstream non-posted read is sent to a device that must first send an upstream non-posted
read before it can complete the downstream read.
In both cases, a locked transaction causes the upstream channel to be blocked, causing the deadlock
condition.
<b>Potential Effect on System</b>
The system fails due to a bus deadlock.</font color=green>
<font color=green><b>94 Sequential Prefetch Feature May Cause Incorrect Processor Operation</b>
<b>Description</b>
On an instruction cache miss, the sequential prefetch mechanism may enable the early prefetch of the
next sequential cache line. Under a highly specific set of internal pipeline conditions this mechanism
may cause the processor to hang or execute incorrect code in 64-bit systems running 32-bit
compatibility mode applications.
<b>Potential Effect on System</b>
Processor may deadlock or execute incorrect code.</font color=green>
<font color=green><b>97 128-Bit Streaming Stores May Cause Coherency Failure</b>
<b>Description</b>
Under a specific set of internal pipeline conditions, stale data may be left in the L1 cache when a 128-
bit streaming store (MOVNT*) to a writeback (WB) memory type misses in the L1 data cache and
both L1 and L2 TLBs.
<b>Potential Effect on System</b>
Memory coherence failures leading to unpredictable operation.</font color=green>
Don't shoot the messenger. This is all straight out of AMD's documentation. If you own an Opteron or Athlon 64 I would highly suggest that you look up what bugs you are potentially affected by and see about trying to implement any of AMD's suggested workarounds. Better safe than sorry.
<A HREF="http://ars.userfriendly.org/cartoons/?id=20031017" target="_new">Then what's your poison of choice?
Soymilk. I was raised on the stuff.
Ah. What's it made of?
Soy.
Is that soy as in soylent green?</A>