In my limited(n=1) experience, these large non-binary modules seem to have pretty loose secondary timings that you can try to tighten by hand. But that's coming from someone whose Corsair 2x48GB 6000C30 kits - same 3GB Hynix M-die as in the review - won't stabilize at 6400, even with an uncomfortable overvolt and VSoC pegged to 1.3v on a 7800X3D.
I made it stable at tRAS=48 and tRCD=500, getting to 64ns on AIDA64 latency benchmark (from 79ns(!) on stock A-XMP) with 1.36V VDD and 1.1V SoC and called it a day, after three days of trying and three more of various memory stress tests. In retrospect, that probably had as much to do with the processor not stabilizing at 2133MHz FCLK, as well.
Perhaps with a more detailed debug display or port I might have investigated more, but just trying to duplicate some of the settings people had reported success with, generally resulted in hung memory even without increasing the RAM clocks. After two days of experimentation I simply asked myself if I could live better with the bandwidth constraints or the reduced amount of RAM. And since I'm only replacing one of three 128GB systems I opted for a RAM reduction, which need not be final if I decide to swallow the bandwidth pill.
I'm just surprised that I found so little talk about how much things have changed for DDR5 in 2DPC scenarios, it was really all centered on the price difference not the capacity issues.
And on one of my Ryzen 5950X systems I had actually started with only 1DPC of DD4-3200 ECC and upgraded later, superficially the same Kingston DIMMs but on closer inspections they were even mixed vendors (Samsung & Hynix), yet work seamlessly together mixed in both channels without issue there.
Considering that this kit costed more than the V-Cache processor, I'm in no haste to not make it last as long as possible.
I seem to recall someone mentioning how they stabilized a 4x32GB setup at 6000C30 somewhere, with ZenTiming screenshot, when I researched what to do with mine.
Hopefully Ryzen 9000 would eventually come with a stronger memory controller, and maybe more IF bandwidth as well. Or maybe we'd finally get CXL on PC, which could be a good use for PCIe 5.0 bandwidths at long last.
I've seen those screenshots and tried replicating them, mostly in terms of termination Ohms and voltages, without raising the clocks just yet, but it just stopped the modules from working at all which are using all Hynix dies, too.
I'd like to see a bit more in-depth reporting on Intel vs. AMD here, just to understand how much of it is barriers of physics vs. limiting silicon budget engineering.
When you push signals at these speeds across copper traces, every millimeter obviously counts. But this steep a penalty for 2DPC seemed somewhat novel, until I remembered that with Kabini, there was a somewhat similar issue at DDR3-2400, which just wouldn't work with 2DPC.
In both cases AMD's spec clearly present the limitations, and with Kabini I remember that they just couldn't be overcome.
So perhaps I've just been "misled" by the AM5000 series doing so much better in 2DPC than before and after...
My initial fear was that ASUS had simply "cheaped out" on testing high-capacity 2DPC modules, given the gamer focus of these entry level boards.
But then I saw the story repeating itself across vendors and now my impression is that while you may luck out with 1DPC bandwiths on a 2DPC setup, you are almost guaranteed to pay for it in safety margin and in my line of work I at least need to be able to choose between "safe" and "fast", depending on the workload and ideally at run-time.
That would a rather welcome feature, being able to activate the 2nd set of modules only when I'm running LLMs or extra VMs, while I could opt for speed otherwise.
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