News Kioxia Demos HLC 3D NAND and Talks About OLC NAND

2Be_or_Not2Be

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Aug 23, 2013
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I like the research - testing the limits of what might be possible. But I'd much rather research go into technology that is an upgrade performance-wise, than yet another downgrade in both performance & durability.
 

1_rick

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Mar 7, 2014
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" To store six bits per cell (HLC), that cell has to hold 2^6, or 64 voltage levels. "

Well, not quite. I get what you're saying, but it's poorly written. It's more accurate to say "to be able to store n bits per cell, the cell has to be able to reliably store and distinguish between 2^n different voltage levels, any one of which the cell will maintain at any given time." If it can't maintain the voltage within whatever precision it requires, or it can't properly read the voltage, it will lose data. Hexabit cells would have 64 different potential voltages, with a difference of 0.078 volts between any two adjacent values. So storing a 7 (000111) is a voltage of 0.546875, and an 8 (001000) is .0625v. If the cell degrades so that it can't maintain the voltage with the required precision (e.g., it's storing 0.6v--or it's storing 0.62v, but the reading circuit thinks it's got an 0.6v) then it can't accurately remember whether it's got a 7, an 8, or something else.)

Edit: admittedly, subsequent paragraphs do a better job of explaining it. To give a more specific example, it's common that 5v logic chips (like 7400-series TTL) might specify that a voltage under 0.8v is a logic 0 and anything over 2v is a logic 1 (I got those values from the datasheet for a 74193). A voltage of 1.5 is out of spec and indeterminate--if you feed that into it, you can't predict what will come out.)
 

ravewulf

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Oct 20, 2008
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I'd rather focus on the durability aspect and scale up in terms of layers or additional PCB space for chips than increasing how many bits per cell. Either that or change to different materials/technology that can store multiple values without the significant drop in durability we're currently seeing.
 

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