I recently bought these two items from Kingston
http://www.kingston.com/dataSheets/KVR13R9D4K3_48.pdf
and
http://www.kingston.com/dataSheets/KVR13R9D4_16.pdf
They have identical specs but someone at Kingston told me that they might not work together. Before I decide to return them I wanted to check this out with you guys:
The 48GB kit (3x16G) is made with these chipsets
DDR3 SDRAM
H5TC4G43AFR
The H5TC4G43AFR-xxA, H5TC4G83AFR-xxA and H5TC4G63AFR-xxA are a 4Gb low power Double Data Rate III (DDR3L) Synchronous DRAM, ideally suited for the main memory applications which requires large memory density, high bandwidth and low power operation at 1.35V. DDR3L SDRAM provides backward compatibility with the 1.5V DDR3 based environment without any changes. (Please refer to the SPD information for details.)
SK hynix 4Gb DDR3L SDRAMs offer fully synchronous operations referenced to both rising and falling edges of the clock. While all addresses and control inputs are latched on the rising edges of the CK (falling edges of the CK), Data, Data strobes and Write data masks inputs are sampled on both rising and falling edges of it. The data paths are internally pipelined and 8-bit prefetched to achieve very high bandwidth.
Features
The other one (1x16GB) is made with this memory chip:
DDR3 SDRAM
H5TC4G43MFR
The H5TC4G43MFR-xxA, H5TC4G83MFR-xxA and H5TC4G63MFR-xxA are a 4Gb low power Double Data Rate III (DDR3L) Synchronous DRAM, ideally suited for the main memory applications which requires large memory density, high bandwidth and low power operation at 1.35V. SK hynix DDR3L SDRAM provides back-ward compatibility with the 1.5V DDR3 based environment without any changes. (Please refer to the SPD information for details.)
SK hynix 4Gb DDR3L SDRAMs offer fully synchronous operations referenced to both rising and falling edges of the clock. While all addresses and control inputs are latched on the rising edges of the clock (falling edges of the clock), data, data strobes and write data masks inputs are sampled on both rising and falling edges of it. The data paths are internally pipelined and 8-bit prefetched to achieve very high bandwidth.
Features
I have marked the difference with red
Complete specs here
https://www.skhynix.com/inc/pdfDownload.jsp?path=/datasheet/pdf/dram/Computing_DDR3L_H5TC4G4(8_6)3MFR(Rev1.0).pdf
https://www.skhynix.com/inc/pdfDownload.jsp?path=/datasheet/pdf/dram/Computing_DDR3L_H5TC4G4(8_6)3AFR(Rev1.0).pdf
Will they work together on my MB (KGP-D16 with two processors installed)?
http://www.kingston.com/dataSheets/KVR13R9D4K3_48.pdf
and
http://www.kingston.com/dataSheets/KVR13R9D4_16.pdf
They have identical specs but someone at Kingston told me that they might not work together. Before I decide to return them I wanted to check this out with you guys:
The 48GB kit (3x16G) is made with these chipsets
DDR3 SDRAM
H5TC4G43AFR
The H5TC4G43AFR-xxA, H5TC4G83AFR-xxA and H5TC4G63AFR-xxA are a 4Gb low power Double Data Rate III (DDR3L) Synchronous DRAM, ideally suited for the main memory applications which requires large memory density, high bandwidth and low power operation at 1.35V. DDR3L SDRAM provides backward compatibility with the 1.5V DDR3 based environment without any changes. (Please refer to the SPD information for details.)
SK hynix 4Gb DDR3L SDRAMs offer fully synchronous operations referenced to both rising and falling edges of the clock. While all addresses and control inputs are latched on the rising edges of the CK (falling edges of the CK), Data, Data strobes and Write data masks inputs are sampled on both rising and falling edges of it. The data paths are internally pipelined and 8-bit prefetched to achieve very high bandwidth.
Features
VDD=VDDQ=1.35V + 0.100 / - 0.067V
Fully differential clock inputs (CK, CK) operation
Differential Data Strobe (DQS, DQS)
On chip DLL align DQ, DQS and DQS transition with CK transition
DM masks write data-in at the both rising and falling edges of the data strobe
All addresses and control inputs except data, data strobes and data masks latched on the rising edges of the clock
Programmable CAS latency 5, 6, 7, 8, 9, 10, 11, 13 supported
Programmable additive latency 0, CL-1, and CL-2 supported
Programmable CAS Write latency (CWL) = 5, 6, 7, 8, 9
Programmable burst length 4/8 with both nibble sequential and interleave mode
BL switch on the fly
8banks
Average Refresh Cycle (Tcase of 0 oC~ 95oC)
- 7.8 µs at 0oC ~ 85 oC
- 3.9 µs at 85oC ~ 95 oC
JEDEC standard 78ball FBGA(x4/x8), 96ball FBGA(x16)
Driver strength selected by EMRS
Dynamic On Die Termination supported
Asynchronous RESET pin supported
ZQ calibration supported
TDQS (Termination Data Strobe) supported (x8 only)
Write Levelization supported
8 bit pre-fetch
This product in compliance with the RoHS directive.
The other one (1x16GB) is made with this memory chip:
DDR3 SDRAM
H5TC4G43MFR
The H5TC4G43MFR-xxA, H5TC4G83MFR-xxA and H5TC4G63MFR-xxA are a 4Gb low power Double Data Rate III (DDR3L) Synchronous DRAM, ideally suited for the main memory applications which requires large memory density, high bandwidth and low power operation at 1.35V. SK hynix DDR3L SDRAM provides back-ward compatibility with the 1.5V DDR3 based environment without any changes. (Please refer to the SPD information for details.)
SK hynix 4Gb DDR3L SDRAMs offer fully synchronous operations referenced to both rising and falling edges of the clock. While all addresses and control inputs are latched on the rising edges of the clock (falling edges of the clock), data, data strobes and write data masks inputs are sampled on both rising and falling edges of it. The data paths are internally pipelined and 8-bit prefetched to achieve very high bandwidth.
Features
VDD=VDDQ=1.35V + 0.100 / - 0.067V
Fully differential clock inputs (CK, /CK) operation
Differential Data Strobe (DQS, /DQS)
On chip DLL align DQ, DQS and /DQS transition with CK transition
DM masks write data-in at the both rising and falling edges of the data strobe
All addresses and control inputs except data, data strobes and data masks latched on the rising edges of the clock
Programmable CAS latency 6, 7, 8, 9, 10 and 11, 13 supported
Programmable additive latency 0, CL-1, and CL-2 supported
Programmable CAS Write latency (CWL) = 5, 6, 7, 8
Programmable burst length 4/8 with both nibble sequential and interleave mode
BL switch on the fly
8banks
Average Refresh Cycle (Tcase of 0 oC~ 95oC)
- 7.8 µs at 0oC ~ 85 oC
- 3.9 µs at 85oC ~ 95 oC
Auto Self Refresh supported
JEDEC standard 78ball FBGA(x4/x8), 96ball FBGA (x16)
Driver strength selected by EMRS
Dynamic On Die Termination supported
Asynchronous RESET pin supported
ZQ calibration supported
TDQS (Termination Data Strobe) supported (x8 only)
Write Levelization supported
8 bit pre-fetch
This product in compliance with the RoHS directive
I have marked the difference with red
Complete specs here
https://www.skhynix.com/inc/pdfDownload.jsp?path=/datasheet/pdf/dram/Computing_DDR3L_H5TC4G4(8_6)3MFR(Rev1.0).pdf
https://www.skhynix.com/inc/pdfDownload.jsp?path=/datasheet/pdf/dram/Computing_DDR3L_H5TC4G4(8_6)3AFR(Rev1.0).pdf
Will they work together on my MB (KGP-D16 with two processors installed)?