I agree with Linus 100%. We have hardware and software error correction on nearly everything in the PC including SSDs, PCIe bus, and even RAID. But Intel continues to force the consumer to pay their server chip tax to get ECC in the memory controller on the mainstream CPUs. This isn't even a cost issue: you can get ECC in $4 CPUs now. I have not purchased a consumer level Intel system in nearly a decade because of this.Linus Torvalds blasts Intel for strangling the ECC memory market, praises AMD for making it an option on Ryzen platforms.
Linus Torvalds Blasts Intel For Strangling the ECC Memory Market : Read more
I am not sure about DDR5, but there is typically a 2% memory performance impact with ECC in general. This can be negated by larger CPU caches.
Intel has clients which are billion dollar corporations, and as you know, linux is the most widely used operating system in servers in general and dominates, oh you know, all 500 of the top 500 computers on the planet in particular. Perhaps this isnt the hobbyist OS you think it is? In any case. Even Microsoft has said that Linux dominates Azure and their rising contributions confirm this. Why else would they?Maybe Intel (the largest contributor to the Linux codebase) should stop fixing his 2nd banana operating system and let him figure it all out.
I don't know where all this "All DDR 5 has ECC", but that's not the case, and Linus is correct.
A quick clarification on DDR5 ECC: DDR5 chip implements single error correction only (mostly for refresh related cell errors), there is no detection for >1 error within one internal array read (128 bits internally). There is no provision for a DRAM supplier to change the level of ecc correction depending on IC process/yield in the spec (they can not implement SECDED instead of SEC for DDR5).Your comment made me dig deeper, and I was surprised to find that you are correct - with some clarity needed.
Due to the lower voltages and very low CMOS threshold voltages being used in DDR5, they are expecting significant numbers of poor cell reads, much like happens with SSD cells. The solution they are using was to add on chip ECC just like with SSDs. The implementation can vary from vendor to vendor, so they can change to what level of ECC that they want to use depending upon IC process yield and intended error reliability. Again, this is much like SSDs. SSDs for servers are more expensive, and also more reliable. Hence the need for ReFS and ZFS file systems (software level error correction within the file system).
So this is chip level ECC. Only.
The actual DDR5 spec also allows for ECC on the memory bus, just like is presently use for previous DDR4 on back through the original DDR. This allows for catching bad reads throughout the motherboard bus all the way to the CPU. This ECC level is optional, if I read the DDR5 spec correctly. This is the same ECC scheme used as before on the system DRAM bus.
I have to say I am bummed at this. They could have used a system wide solution to improve overall robustness, and they missed the opportunity. Hopefully, they did spend some time on the bus voltage control and noise, as well as impedance controls to improve the signal integrity.
For more reading, here is an article on Anandtech with good comments at the end:
And yes - shame on Intel.