Max # of PCI Express Lanes

[Kalibek]

So I just built a new PC with i5 6600k and obviously I have GPU - AMD RX480 which is 3.0x16 and one m.2 nvme ssd is coming my way, which is also PCI Express Gen3 x4, and i5 supports only 16 lanes, does it mean I already maxed it out and will not be able to use m.2 ssd on its full power?

 

[faalin]

depending on what motherboard you have it may drop your rx480 down to 8x mode so it can give some lanes to the ssd. Read your manual and it should tell you where to plug things in for best performance

 

[Kalibek]

depending on what motherboard you have it may drop your rx480 down to 8x mode so it can give some lanes to the ssd. Read your manual and it should tell you where to plug things in for best performance

thanks,
I have Gigabyte Z170n gaming 5 mini itx mobo


Expansion Slots
1 x PCI Express x16 slot, running at x16
(The PCIEX16 slot conforms to PCI Express 3.0 standard.)

Storage Interface
1 x M.2 Socket 3 connector on the back of the motherboard (Socket 3, M key, type 2260/2280 SATA & PCIe x4/x2/x1 SSD support)

 

[matt4x4]

Z170 should have 20 x 3.0
The CPU itself has PCIe lanes too.

 

[Samer1970]

The M2 is connected to the Chipset with 4 PCIe 3.0 lanes . and not to the CPU Lanes .

dont worry , your Graphics card will not drop to x8 mode

 

[matt4x4]

http://www.tomshardware.com/forum/id-2604000/h170-z170-motherboards.html

H170 does *not* allow you to split the CPU PCIe lanes. So on H170 boards you'll get 1xPCIe 3.0 x16, and any further PCIe slots will be using lanes from chipset which are limited to a maximum of x4 lanes. That means NO SLI. Although CFX will technically work, it's not ideal and with high end hardware not a good idea.

Z170 on the other hand allows boards to split CPU PCIe lanes, providing two x8 slots, enabling multi-GPU options. To be clear, not all Z170 boards will actually implement this, but the fact is they can, whereas H170 boards cannot.

H170 boards can still offer great value for money as long as they're recognised as single-GPU only boards. Sorry again for reviving this thread, just felt it was an important bit of info for people trying to get their heads around these sometimes confusing chipset implementations.