My tuned DDR5 runs at a latency of 55ns. Which isn't great, but seems fairly decent. If these new Mr.DIMMs can knock 40% off of that it would put the latency in L3 cache range.
That sounds too good to be true. But if it is then it would also change how CPUs are built with large L2 taking priority and large L3 becoming irrelevant.
Edit: The Dec 2021 Micron DDR5 DIMMS I have could only do about 65ns latency so 60% of that drops it to 39ns tuned, which is not quite as good as L3 anymore. Hopefully Hynix figures out a way to make these.