For 1P systems these are very rare cases like suspend/resume where latency does not matter already.Makes me wonder how much lag is introduced if the cache needs to be flushed.
Just curious what is your background with tech? Are you an engineer or computer science guy?For 1P systems these are very rare cases like suspend/resume where latency does not matter already.
Would probably be on a scale of one to few seconds for completely dirty L3 cache (which is rare as well).
For xP SMP systems, cross node memory access will prevent need to flush L3 as well.
Memory shared with devices and accessible by devices is usually set up as writethrough or uncached and flushed manually/in ranges as required.
All in all I don't see any reasonable use cases where flushing whole L3 is a necessity, or would be of any concern actually
Well, not a hardware person per se, meaning not involved in any hardware development. Do understand how hardware works though, not on electrical level though, but on logical level.Just curious what is your background with tech? Are you an engineer or computer science guy?