MIT researchers developed a new method that allows the layers of interconnect patterns to "self-assemble" into much finer pattern lines. This new method should make it more cost-effective to go below the 10nm process node, compared to EUV lithography.
MIT Researchers Reveal More Efficient Way To Build Chips Below The 10nm Process : Read more
MIT Researchers Reveal More Efficient Way To Build Chips Below The 10nm Process : Read more