According to <A HREF="http://www.theinquirer.net/?article=18759" target="_new">the inquirer</A>, montecito, Intel's new dual-core montecito due to be launched roughly together with all the other dual-core products next year, will use dedicated 667Mhz front-side-busses for each processor, each with 128 bit width, for a total of 10.6GB/s bandwidth for each processor.
A hypothetical two-way montecito would then have four cores, 48MB cache, two 667Mhz (or possibly 800Mhz, if they can get it to work with that) FSBs and quad-channel DDR2-667 (at least) or DDR2-800 (probably depending on availability and evolution of DDR2). The quad DDR2-667 would be 21.2GB/s wide and DDR2-800 would be 25.6GB/s wide.
Quite a lot better than the simple 6.4GB/s for the whole system on a current four-CPU, four-core Itanium system!
I wonder if this idea will also drop to the Xeon lineup?...
A hypothetical two-way montecito would then have four cores, 48MB cache, two 667Mhz (or possibly 800Mhz, if they can get it to work with that) FSBs and quad-channel DDR2-667 (at least) or DDR2-800 (probably depending on availability and evolution of DDR2). The quad DDR2-667 would be 21.2GB/s wide and DDR2-800 would be 25.6GB/s wide.
Quite a lot better than the simple 6.4GB/s for the whole system on a current four-CPU, four-core Itanium system!
I wonder if this idea will also drop to the Xeon lineup?...