Hello everyone. I recently sent my computer to cleaning, changing the thermal paste on my PC, and replace a rear fan on my cabinet, but since it is back I noticed something weird. Even just opening some browser tabs the CPU heats to 60º-70º and when I try anything a little more demanding it peaks to 90º-100º (Just like opening a VM or a simple game). I noticed looking at the task manager that the CPU usage is not high, less than 30% is enough to create those peeks. At 10% it is already going to 70º-80º!
I would really appreciate it if anyone can give me some help with it. I run an HViNFO Report last week before doing the repairs and another one today and the most significant difference I saw on those reports about the CPU is the IccMax (which I don't know what it is. If anyone can help me understand). Please I'll be glad to get any help on finding the issue, I'll paste the reports highlighting the differences here if anyone could help.
The report on the CPU before the problem:
And the report on CPU after the problem:
I would really appreciate it if anyone can give me some help with it. I run an HViNFO Report last week before doing the repairs and another one today and the most significant difference I saw on those reports about the CPU is the IccMax (which I don't know what it is. If anyone can help me understand). Please I'll be glad to get any help on finding the issue, I'll paste the reports highlighting the differences here if anyone could help.
The report on the CPU before the problem:
Intel Core i7-7700 |
[General Information] | ||
Processor Name: | Intel Core i7-7700 | |
Original Processor Frequency: | 3600.0 MHz | |
Original Processor Frequency [MHz]: | 3600 | |
CPU ID: | 000906E9 | |
CPU Brand Name: | Intel(R) Core(TM) i7-7700 CPU @ 3.60GHz | |
CPU Vendor: | GenuineIntel | |
CPU Stepping: | B0 | |
CPU Code Name: | Kaby Lake-S | |
CPU Technology: | 14 nm | |
CPU S-Spec: | SR338 | |
CPU Thermal Design Power (TDP): | 65.0 W | |
CPU Power Limits (Max): | Power = Unlimited, Time = Unlimited | |
CPU Power Limit 1 - Long Duration: | Power = 65.00 W, Time = 8.00 sec [Unlocked] | |
CPU Power Limit 2 - Short Duration: | Power = 81.25 W, Time = 2.44 ms [Unlocked] | |
CPU Max. Junction Temperature (Tj,max): | 100 °C | |
CPU Type: | Production Unit | |
CPU Platform: | Socket H4 (LGA1151) | |
Microcode Update Revision: | B4 | |
Number of CPU Cores: | 4 | |
Number of Logical CPUs: | 8 | |
[Operating Points] | ||
CPU LFM (Minimum): | 800.0 MHz = 8 x 100.0 MHz | |
CPU HFM (Base): | 3600.0 MHz = 36 x 100.0 MHz | |
CPU Turbo Max: | 4200.0 MHz = 42 x 100.0 MHz [Unlocked] | |
Turbo Ratio Limits - IA/SSE: | 42x (1c), 41x (2-3c), 40x (4c) | |
Turbo Ratio Limits - AVX2, Resolved: | 42x (1c), 41x (2-3c), 40x (4c) | |
CPU Current: | 4090.0 MHz = 41 x 99.8 MHz @ 1.1821 V | |
LLC/Ring Maximum: | 3900.0 MHz = 39.00 x 100.0 MHz | |
LLC/Ring Current: | 3790.7 MHz = 38.00 x 99.8 MHz | |
System Agent Current: | 997.6 MHz = 10.00 x 99.8 MHz | |
CPU Bus Type: | Intel Direct Media Interface (DMI) v3.0 | |
Maximum DMI Link Speed: | 8.0 GT/s | |
Current DMI Link Speed: | 5.0 GT/s | |
Ring to Core Offset: | Enabled | |
[IA Overclocking] | ||
Voltage Offset: | Supported | |
Voltage Override: | Supported | |
Ratio Overclocking: | Not Supported | |
Fused Ratio Limit: | 42x | |
OC Ratio Limit: | N/A | |
Voltage Mode: | Interpolative | |
Voltage Offset: | 0 mV | |
IccMax: | 90.00 A | |
[GT (Slice) Overclocking] | ||
Voltage Offset: | Supported | |
Voltage Override: | Supported | |
Ratio Overclocking: | Not Supported | |
Fused Ratio Limit: | 23x | |
OC Ratio Limit: | N/A | |
Voltage Mode: | Interpolative | |
Voltage Offset: | 0 mV | |
IccMax: | 101.00 A | |
[CLR (CBo/LLC/Ring) Overclocking] | ||
Voltage Offset: | Supported | |
Voltage Override: | Supported | |
Ratio Overclocking: | Not Supported | |
Fused Ratio Limit: | 39x | |
OC Ratio Limit: | N/A | |
Voltage Mode: | Interpolative | |
Voltage Offset: | 0 mV | |
IccMax: | 90.00 A | |
[GT (Unslice) Overclocking] | ||
Voltage Offset: | Supported | |
Voltage Override: | Supported | |
Ratio Overclocking: | Not Supported | |
Fused Ratio Limit: | 23x | |
OC Ratio Limit: | N/A | |
Voltage Mode: | Interpolative | |
Voltage Offset: | 0 mV | |
IccMax: | 101.00 A | |
[Uncore/SA Overclocking] | ||
Voltage Offset: | Supported | |
Voltage Override: | Not Supported | |
Ratio Overclocking: | Not Supported | |
Fused Ratio Limit: | N/A | |
OC Ratio Limit: | N/A | |
Voltage Mode: | Interpolative | |
Voltage Offset: | 0 mV | |
IccMax: | 20.00 A | |
[Cache and TLB] | ||
L1 Cache: | Instruction: 4 x 32 KBytes, Data: 4 x 32 KBytes | |
L2 Cache: | Integrated: 4 x 256 KBytes | |
L3 Cache: | 8 MBytes | |
Instruction TLB: | 2MB/4MB Pages, Fully associative, 8 entries | |
Data TLB: | 4 KB Pages, 4-way set associative, 64 entries | |
[Standard Feature Flags] | ||
FPU on Chip | Present | |
Enhanced Virtual-86 Mode | Present | |
I/O Breakpoints | Present | |
Page Size Extensions | Present | |
Time Stamp Counter | Present | |
Pentium-style Model Specific Registers | Present | |
Physical Address Extension | Present | |
Machine Check Exception | Present | |
CMPXCHG8B Instruction | Present | |
APIC On Chip / PGE (AMD) | Present | |
Fast System Call | Present | |
Memory Type Range Registers | Present | |
Page Global Feature | Present | |
Machine Check Architecture | Present | |
CMOV Instruction | Present | |
Page Attribute Table | Present | |
36-bit Page Size Extensions | Present | |
Processor Number | Not Present | |
CLFLUSH Instruction | Present | |
Debug Trace and EMON Store | Present | |
Internal ACPI Support | Present | |
MMX Technology | Present | |
Fast FP Save/Restore (IA MMX-2) | Present | |
Streaming SIMD Extensions | Present | |
Streaming SIMD Extensions 2 | Present | |
Self-Snoop | Present | |
Multi-Threading Capable | Present | |
Automatic Clock Control | Present | |
IA-64 Processor | Not Present | |
Signal Break on FERR | Present | |
Virtual Machine Extensions (VMX) | Present | |
Safer Mode Extensions (Intel TXT) | Present | |
Streaming SIMD Extensions 3 | Present | |
Supplemental Streaming SIMD Extensions 3 | Present | |
Streaming SIMD Extensions 4.1 | Present | |
Streaming SIMD Extensions 4.2 | Present | |
AVX Support | Present | |
Fused Multiply Add (FMA) | Present | |
Carryless Multiplication (PCLMULQDQ)/GFMUL | Present | |
CMPXCHG16B Support | Present | |
MOVBE Instruction | Present | |
POPCNT Instruction | Present | |
XSAVE/XRSTOR/XSETBV/XGETBV Instructions | Present | |
XGETBV/XSETBV OS Enabled | Present | |
Float16 Instructions | Present | |
AES Cryptography Support | Present | |
Random Number Read Instruction (RDRAND) | Present | |
Extended xAPIC | Present | |
MONITOR/MWAIT Support | Present | |
Thermal Monitor 2 | Present | |
Enhanced SpeedStep Technology | Present | |
L1 Context ID | Not Present | |
Send Task Priority Messages Disabling | Present | |
Processor Context ID | Present | |
Direct Cache Access | Not Present | |
TSC-deadline Timer | Present | |
Performance/Debug Capability MSR | Present | |
IA32 Debug Interface Support | Present | |
64-Bit Debug Store | Present | |
CPL Qualified Debug Store | Present | |
[Extended Feature Flags] | ||
64-bit Extensions | Present | |
RDTSCP and TSC_AUX Support | Present | |
1 GB large page support | Present | |
No Execute | Present | |
SYSCALL/SYSRET Support | Present | |
Bit Manipulation Instructions Set 1 | Present | |
Bit Manipulation Instructions Set 2 | Present | |
Advanced Vector Extensions 2 (AVX2) | Present | |
Advanced Vector Extensions 512 (AVX-512) | Not Present | |
AVX-512 Prefetch Instructions | Not Present | |
AVX-512 Exponential and Reciprocal Instructions | Not Present | |
AVX-512 Conflict Detection Instructions | Not Present | |
AVX-512 Doubleword and Quadword Instructions | Not Present | |
AVX-512 Byte and Word Instructions | Not Present | |
AVX-512 Vector Length Extensions | Not Present | |
AVX-512 52-bit Integer FMA Instructions | Not Present | |
Secure Hash Algorithm (SHA) Extensions | Not Present | |
Software Guard Extensions (SGX) Support | Present | |
Supervisor Mode Execution Protection (SMEP) | Present | |
Supervisor Mode Access Prevention (SMAP) | Present | |
Hardware Lock Elision (HLE) | Present | |
Restricted Transactional Memory (RTM) | Present | |
Memory Protection Extensions (MPX) | Present | |
Read/Write FS/GS Base Instructions | Present | |
Enhanced Performance String Instruction | Present | |
INVPCID Instruction | Present | |
RDSEED Instruction | Present | |
Multi-precision Add Carry Instructions (ADX) | Present | |
PCOMMIT Instructions | Not Present | |
CLFLUSHOPT Instructions | Present | |
CLWB Instructions | Not Present | |
TSC_THREAD_OFFSET | Present | |
Platform Quality of Service Monitoring (PQM) | Not Present | |
Platform Quality of Service Enforcement (PQE) | Not Present | |
FPU Data Pointer updated only on x87 Exceptions | Not Present | |
Deprecated FPU CS and FPU DS | Present | |
Intel Processor Trace | Present | |
PREFETCHWT1 Instruction | Not Present | |
AVX-512 Vector Bit Manipulation Instructions | Not Present | |
AVX-512 Vector Bit Manipulation Instructions 2 | Not Present | |
AVX-512 Galois Fields New Instructions | Not Present | |
AVX-512 Vector AES | Not Present | |
AVX-512 Vector Neural Network Instructions | Not Present | |
AVX-512 Bit Algorithms | Not Present | |
AVX-512 Carry-Less Multiplication Quadword (VPCLMULQDQ) | Not Present | |
AVX-512 Vector POPCNT (VPOPCNTD/VPOPCNTQ) | Not Present | |
User-Mode Instruction Prevention | Not Present | |
Protection Keys for User-mode Pages | Not Present | |
OS Enabled Protection Keys | Not Present | |
Wait and Pause Enhancements (WAITPKG) | Not Present | |
Total Memory Encryption | Not Present | |
Read Processor ID | Not Present | |
Cache Line Demote | Not Present | |
MOVDIRI: Direct Stores | Not Present | |
MOVDIR64B: Direct Stores | Not Present | |
ENQCMD: Enqueue Stores | Not Present | |
SGX Launch Configuration | Not Present | |
Control-Flow Enforcement Technology (CET) Shadow Stack | Not Present | |
AVX-512 4 x Vector Neural Network Instructions Word Variable Precision | Not Present | |
AVX-512 4 x Fused Multiply Accumulation Packed Single Precision | Not Present | |
Fast Short REP MOV | Not Present | |
AVX-512 VP2INTERSECT Support | Not Present | |
MD_CLEAR Support | Present | |
Hybrid Processor | Not Present | |
Platform Configuration (PCONFIG) | Not Present | |
Indirect Branch Restricted Speculation (IBRS), Indirect Branch Predictor Barrier (IBPB) | Present | |
Single Thread Indirect Branch Predictors (STIBP) | Present | |
L1D_FLUSH Support | Present | |
IA32_ARCH_CAPABILITIES MSR | Not Present | |
IA32_CORE_CAPABILITIES MSR | Not Present | |
Speculative Store Bypass Disable (SSBD) | Present | |
Control-Flow Enforcement Technology (CET) Indirect Branch Tracking | Not Present | |
Advanced Matrix Extensions (AMX) Tile Architecture | Not Present | |
Advanced Matrix Extensions (AMX) bfloat16 Support | Not Present | |
Advanced Matrix Extensions (AMX) 8-bit Integer Operations | Not Present | |
AVX-512 BFLOAT16 Instructions | Not Present | |
[Enhanced Features] | ||
Thermal Monitor 1: | Supported, Enabled | |
Thermal Monitor 2: | Supported, Enabled | |
Enhanced Intel SpeedStep (GV3): | Supported, Enabled | |
Bi-directional PROCHOT#: | Enabled | |
Extended Auto-HALT State C1E: | Enabled | |
MLC Streamer Prefetcher | Supported, Enabled | |
MLC Spatial Prefetcher | Supported, Enabled | |
DCU Streamer Prefetcher | Supported, Enabled | |
DCU IP Prefetcher | Supported, Enabled | |
Intel Dynamic Acceleration (IDA) Technology: | Not Supported | |
Intel Dynamic FSB Switching: | Not Supported | |
Intel Turbo Boost Technology: | Supported, Enabled | |
Programmable Ratio Limits: | Supported, Disabled | |
Programmable TDC/TDP Limits: | Supported, Disabled | |
Hardware Duty Cycling: | Supported, Enabled | |
[CPU SKU Features] | ||
Display HD Audio: | Supported | |
DMI x4 Width: | Supported | |
DRAM ECC: | Not Supported | |
VT-d: | Supported | |
DMI in Gen2 Mode: | Supported | |
PEG in Gen2 Mode: | Supported | |
1N Mode DDR Timings: | Supported | |
Camarillo (DTT) Device: | Supported | |
2 DIMMs per Channel: | Not Supported | |
X2APIC: | Supported | |
Dual Memory Channel: | Supported | |
Integrated GPU (IGD): | Enabled | |
DDR Overclocking: | Disabled | |
Overclocking by DSKU: | Disabled | |
DDR3L: | Supported | |
Maximum Memory Size per Channel: | 64 GB (unlimited) | |
Overclocking: | Disabled | |
Hyper-Threading (SMT): | Supported | |
Additive Graphics: | Supported | |
Additive Graphics: | Enabled | |
PCIe Gen 3: | Supported | |
DMI Gen 3: | Supported | |
HDCP: | Supported | |
DDR4: | Supported | |
LPDDR3: | Not Supported | |
BCLK OC Limit: | 100 MHz | |
Maximum Supported LPDDR3 Frequency: | 1600 MHz | |
Maximum Supported DDR4 Frequency: | 1200 MHz | |
SVID Status: | Enabled | |
[Voltage Regulator (SVID)] | ||
VCC VR: | ON Semi (0x5b), IMVP8 | |
VR Thermal Sensor: | Supported | |
[Memory Ranges] | ||
Maximum Physical Address Size: | 39-bit (512 GBytes) | |
Maximum Virtual Address Size: | 48-bit (256 TBytes) | |
[MTRRs] | ||
Range E0000000-100000000 (3584MB-4096MB) Type: | Uncacheable (UC) | |
Range D0000000-E0000000 (3328MB-3584MB) Type: | Uncacheable (UC) | |
Range C8000000-D0000000 (3200MB-3328MB) Type: | Uncacheable (UC) |
And the report on CPU after the problem:
Intel Core i7-7700 |
[General Information] | ||
Processor Name: | Intel Core i7-7700 | |
Original Processor Frequency: | 3600.0 MHz | |
Original Processor Frequency [MHz]: | 3600 | |
CPU ID: | 000906E9 | |
CPU Brand Name: | Intel(R) Core(TM) i7-7700 CPU @ 3.60GHz | |
CPU Vendor: | GenuineIntel | |
CPU Stepping: | B0 | |
CPU Code Name: | Kaby Lake-S | |
CPU Technology: | 14 nm | |
CPU S-Spec: | SR338 | |
CPU Thermal Design Power (TDP): | 65.0 W | |
CPU Power Limits (Max): | Power = Unlimited, Time = Unlimited | |
CPU Power Limit 1 - Long Duration: | Power = Unlimited, Time = 8.00 sec [Unlocked] | |
CPU Power Limit 2 - Short Duration: | Power = Unlimited, Time = 2.44 ms [Unlocked] | |
CPU Max. Junction Temperature (Tj,max): | 100 °C | |
CPU Type: | Production Unit | |
CPU Platform: | Socket H4 (LGA1151) | |
Microcode Update Revision: | B4 | |
Number of CPU Cores: | 4 | |
Number of Logical CPUs: | 8 | |
[Operating Points] | ||
CPU LFM (Minimum): | 800.0 MHz = 8 x 100.0 MHz | |
CPU HFM (Base): | 3600.0 MHz = 36 x 100.0 MHz | |
CPU Turbo Max: | 4200.0 MHz = 42 x 100.0 MHz [Unlocked] | |
Turbo Ratio Limits - IA/SSE: | 42x (1c), 41x (2-3c), 40x (4c) | |
Turbo Ratio Limits - AVX2, Resolved: | 42x (1c), 41x (2-3c), 40x (4c) | |
CPU Current: | 4102.0 MHz = 41 x 100.0 MHz @ 1.2240 V | |
LLC/Ring Maximum: | 3900.0 MHz = 39.00 x 100.0 MHz | |
LLC/Ring Current: | 3801.9 MHz = 38.00 x 100.0 MHz | |
System Agent Current: | 1000.5 MHz = 10.00 x 100.0 MHz | |
CPU Bus Type: | Intel Direct Media Interface (DMI) v3.0 | |
Maximum DMI Link Speed: | 8.0 GT/s | |
Current DMI Link Speed: | 5.0 GT/s | |
Ring to Core Offset: | Enabled | |
[IA Overclocking] | ||
Voltage Offset: | Supported | |
Voltage Override: | Supported | |
Ratio Overclocking: | Not Supported | |
Fused Ratio Limit: | 42x | |
OC Ratio Limit: | N/A | |
Voltage Mode: | Interpolative | |
Voltage Offset: | 0 mV | |
IccMax: | 255.50 A | |
[GT (Slice) Overclocking] | ||
Voltage Offset: | Supported | |
Voltage Override: | Supported | |
Ratio Overclocking: | Not Supported | |
Fused Ratio Limit: | 23x | |
OC Ratio Limit: | N/A | |
Voltage Mode: | Interpolative | |
Voltage Offset: | 0 mV | |
IccMax: | 255.50 A | |
[CLR (CBo/LLC/Ring) Overclocking] | ||
Voltage Offset: | Supported | |
Voltage Override: | Supported | |
Ratio Overclocking: | Not Supported | |
Fused Ratio Limit: | 39x | |
OC Ratio Limit: | N/A | |
Voltage Mode: | Interpolative | |
Voltage Offset: | 0 mV | |
IccMax: | 255.50 A | |
[GT (Unslice) Overclocking] | ||
Voltage Offset: | Supported | |
Voltage Override: | Supported | |
Ratio Overclocking: | Not Supported | |
Fused Ratio Limit: | 23x | |
OC Ratio Limit: | N/A | |
Voltage Mode: | Interpolative | |
Voltage Offset: | 0 mV | |
IccMax: | 255.50 A | |
[Uncore/SA Overclocking] | ||
Voltage Offset: | Supported | |
Voltage Override: | Not Supported | |
Ratio Overclocking: | Not Supported | |
Fused Ratio Limit: | N/A | |
OC Ratio Limit: | N/A | |
Voltage Mode: | Interpolative | |
Voltage Offset: | 0 mV | |
IccMax: | 20.00 A | |
[Cache and TLB] | ||
L1 Cache: | Instruction: 4 x 32 KBytes, Data: 4 x 32 KBytes | |
L2 Cache: | Integrated: 4 x 256 KBytes | |
L3 Cache: | 8 MBytes | |
Instruction TLB: | 2MB/4MB Pages, Fully associative, 8 entries | |
Data TLB: | 4 KB Pages, 4-way set associative, 64 entries | |
[Standard Feature Flags] | ||
FPU on Chip | Present | |
Enhanced Virtual-86 Mode | Present | |
I/O Breakpoints | Present | |
Page Size Extensions | Present | |
Time Stamp Counter | Present | |
Pentium-style Model Specific Registers | Present | |
Physical Address Extension | Present | |
Machine Check Exception | Present | |
CMPXCHG8B Instruction | Present | |
APIC On Chip / PGE (AMD) | Present | |
Fast System Call | Present | |
Memory Type Range Registers | Present | |
Page Global Feature | Present | |
Machine Check Architecture | Present | |
CMOV Instruction | Present | |
Page Attribute Table | Present | |
36-bit Page Size Extensions | Present | |
Processor Number | Not Present | |
CLFLUSH Instruction | Present | |
Debug Trace and EMON Store | Present | |
Internal ACPI Support | Present | |
MMX Technology | Present | |
Fast FP Save/Restore (IA MMX-2) | Present | |
Streaming SIMD Extensions | Present | |
Streaming SIMD Extensions 2 | Present | |
Self-Snoop | Present | |
Multi-Threading Capable | Present | |
Automatic Clock Control | Present | |
IA-64 Processor | Not Present | |
Signal Break on FERR | Present | |
Virtual Machine Extensions (VMX) | Present | |
Safer Mode Extensions (Intel TXT) | Present | |
Streaming SIMD Extensions 3 | Present | |
Supplemental Streaming SIMD Extensions 3 | Present | |
Streaming SIMD Extensions 4.1 | Present | |
Streaming SIMD Extensions 4.2 | Present | |
AVX Support | Present | |
Fused Multiply Add (FMA) | Present | |
Carryless Multiplication (PCLMULQDQ)/GFMUL | Present | |
CMPXCHG16B Support | Present | |
MOVBE Instruction | Present | |
POPCNT Instruction | Present | |
XSAVE/XRSTOR/XSETBV/XGETBV Instructions | Present | |
XGETBV/XSETBV OS Enabled | Present | |
Float16 Instructions | Present | |
AES Cryptography Support | Present | |
Random Number Read Instruction (RDRAND) | Present | |
Extended xAPIC | Present | |
MONITOR/MWAIT Support | Present | |
Thermal Monitor 2 | Present | |
Enhanced SpeedStep Technology | Present | |
L1 Context ID | Not Present | |
Send Task Priority Messages Disabling | Present | |
Processor Context ID | Present | |
Direct Cache Access | Not Present | |
TSC-deadline Timer | Present | |
Performance/Debug Capability MSR | Present | |
IA32 Debug Interface Support | Present | |
64-Bit Debug Store | Present | |
CPL Qualified Debug Store | Present | |
[Extended Feature Flags] | ||
64-bit Extensions | Present | |
RDTSCP and TSC_AUX Support | Present | |
1 GB large page support | Present | |
No Execute | Present | |
SYSCALL/SYSRET Support | Present | |
Bit Manipulation Instructions Set 1 | Present | |
Bit Manipulation Instructions Set 2 | Present | |
Advanced Vector Extensions 2 (AVX2) | Present | |
Advanced Vector Extensions 512 (AVX-512) | Not Present | |
AVX-512 Prefetch Instructions | Not Present | |
AVX-512 Exponential and Reciprocal Instructions | Not Present | |
AVX-512 Conflict Detection Instructions | Not Present | |
AVX-512 Doubleword and Quadword Instructions | Not Present | |
AVX-512 Byte and Word Instructions | Not Present | |
AVX-512 Vector Length Extensions | Not Present | |
AVX-512 52-bit Integer FMA Instructions | Not Present | |
Secure Hash Algorithm (SHA) Extensions | Not Present | |
Software Guard Extensions (SGX) Support | Present | |
Supervisor Mode Execution Protection (SMEP) | Present | |
Supervisor Mode Access Prevention (SMAP) | Present | |
Hardware Lock Elision (HLE) | Present | |
Restricted Transactional Memory (RTM) | Present | |
Memory Protection Extensions (MPX) | Present | |
Read/Write FS/GS Base Instructions | Present | |
Enhanced Performance String Instruction | Present | |
INVPCID Instruction | Present | |
RDSEED Instruction | Present | |
Multi-precision Add Carry Instructions (ADX) | Present | |
PCOMMIT Instructions | Not Present | |
CLFLUSHOPT Instructions | Present | |
CLWB Instructions | Not Present | |
TSC_THREAD_OFFSET | Present | |
Platform Quality of Service Monitoring (PQM) | Not Present | |
Platform Quality of Service Enforcement (PQE) | Not Present | |
FPU Data Pointer updated only on x87 Exceptions | Not Present | |
Deprecated FPU CS and FPU DS | Present | |
Intel Processor Trace | Present | |
PREFETCHWT1 Instruction | Not Present | |
AVX-512 Vector Bit Manipulation Instructions | Not Present | |
AVX-512 Vector Bit Manipulation Instructions 2 | Not Present | |
AVX-512 Galois Fields New Instructions | Not Present | |
AVX-512 Vector AES | Not Present | |
AVX-512 Vector Neural Network Instructions | Not Present | |
AVX-512 Bit Algorithms | Not Present | |
AVX-512 Carry-Less Multiplication Quadword (VPCLMULQDQ) | Not Present | |
AVX-512 Vector POPCNT (VPOPCNTD/VPOPCNTQ) | Not Present | |
User-Mode Instruction Prevention | Not Present | |
Protection Keys for User-mode Pages | Not Present | |
OS Enabled Protection Keys | Not Present | |
Wait and Pause Enhancements (WAITPKG) | Not Present | |
Total Memory Encryption | Not Present | |
Read Processor ID | Not Present | |
Cache Line Demote | Not Present | |
MOVDIRI: Direct Stores | Not Present | |
MOVDIR64B: Direct Stores | Not Present | |
ENQCMD: Enqueue Stores | Not Present | |
SGX Launch Configuration | Not Present | |
Control-Flow Enforcement Technology (CET) Shadow Stack | Not Present | |
AVX-512 4 x Vector Neural Network Instructions Word Variable Precision | Not Present | |
AVX-512 4 x Fused Multiply Accumulation Packed Single Precision | Not Present | |
Fast Short REP MOV | Not Present | |
AVX-512 VP2INTERSECT Support | Not Present | |
MD_CLEAR Support | Present | |
Hybrid Processor | Not Present | |
Platform Configuration (PCONFIG) | Not Present | |
Indirect Branch Restricted Speculation (IBRS), Indirect Branch Predictor Barrier (IBPB) | Present | |
Single Thread Indirect Branch Predictors (STIBP) | Present | |
L1D_FLUSH Support | Present | |
IA32_ARCH_CAPABILITIES MSR | Not Present | |
IA32_CORE_CAPABILITIES MSR | Not Present | |
Speculative Store Bypass Disable (SSBD) | Present | |
Control-Flow Enforcement Technology (CET) Indirect Branch Tracking | Not Present | |
Advanced Matrix Extensions (AMX) Tile Architecture | Not Present | |
Advanced Matrix Extensions (AMX) bfloat16 Support | Not Present | |
Advanced Matrix Extensions (AMX) 8-bit Integer Operations | Not Present | |
AVX-512 BFLOAT16 Instructions | Not Present | |
[Enhanced Features] | ||
Thermal Monitor 1: | Supported, Enabled | |
Thermal Monitor 2: | Supported, Enabled | |
Enhanced Intel SpeedStep (GV3): | Supported, Enabled | |
Bi-directional PROCHOT#: | Enabled | |
Extended Auto-HALT State C1E: | Enabled | |
MLC Streamer Prefetcher | Supported, Enabled | |
MLC Spatial Prefetcher | Supported, Enabled | |
DCU Streamer Prefetcher | Supported, Enabled | |
DCU IP Prefetcher | Supported, Enabled | |
Intel Dynamic Acceleration (IDA) Technology: | Not Supported | |
Intel Dynamic FSB Switching: | Not Supported | |
Intel Turbo Boost Technology: | Supported, Enabled | |
Programmable Ratio Limits: | Supported, Disabled | |
Programmable TDC/TDP Limits: | Supported, Disabled | |
Hardware Duty Cycling: | Supported, Enabled | |
[CPU SKU Features] | ||
Display HD Audio: | Supported | |
DMI x4 Width: | Supported | |
DRAM ECC: | Not Supported | |
VT-d: | Supported | |
DMI in Gen2 Mode: | Supported | |
PEG in Gen2 Mode: | Supported | |
1N Mode DDR Timings: | Supported | |
Camarillo (DTT) Device: | Supported | |
2 DIMMs per Channel: | Not Supported | |
X2APIC: | Supported | |
Dual Memory Channel: | Supported | |
Integrated GPU (IGD): | Enabled | |
DDR Overclocking: | Disabled | |
Overclocking by DSKU: | Disabled | |
DDR3L: | Supported | |
Maximum Memory Size per Channel: | 64 GB (unlimited) | |
Overclocking: | Disabled | |
Hyper-Threading (SMT): | Supported | |
Additive Graphics: | Supported | |
Additive Graphics: | Enabled | |
PCIe Gen 3: | Supported | |
DMI Gen 3: | Supported | |
HDCP: | Supported | |
DDR4: | Supported | |
LPDDR3: | Not Supported | |
BCLK OC Limit: | 100 MHz | |
Maximum Supported LPDDR3 Frequency: | 1600 MHz | |
Maximum Supported DDR4 Frequency: | 1200 MHz | |
SVID Status: | Enabled | |
[Voltage Regulator (SVID)] | ||
VCC VR: | ON Semi (0x5b), IMVP8 | |
VR Thermal Sensor: | Supported | |
[Memory Ranges] | ||
Maximum Physical Address Size: | 39-bit (512 GBytes) | |
Maximum Virtual Address Size: | 48-bit (256 TBytes) | |
[MTRRs] | ||
Range E0000000-100000000 (3584MB-4096MB) Type: | Uncacheable (UC) | |
Range D0000000-E0000000 (3328MB-3584MB) Type: | Uncacheable (UC) | |
Range C8000000-D0000000 (3200MB-3328MB) Type: | Uncacheable (UC) |