New Memory Overclocking Record: 4.56 GHz

[N.Broekhuijsen]

Gigabyte's overclocking team has managed to attain a new memory overclocking record, bringing a set of DDR3 memory up to a frequency of a staggering 4.56 GHz.

New Memory Overclocking Record: 4.56 GHz : Read more

 

[MANOFKRYPTONAK]

This has no real world application, it doesn't make me trust there product more at all. I really hate marketing ploys like this.

 

[Damon Palovaara]

This has no real world application, it doesn't make me trust there product more at all. I really hate marketing ploys like this.

Overclocking is one of the motivational forces behind companies to make better products which will eventually work it's way down to the mainstream.

 

[tom10167]

I thought profits were.

 

[qlum]

And then DDR4 launches and a few years after that this may be your average ram frequency.

 

[MANOFKRYPTONAK]

This has no real world application, it doesn't make me trust there product more at all. I really hate marketing ploys like this.

Overclocking is one of the motivational forces behind companies to make better products which will eventually work it's way down to the mainstream.

Everyone on TH knows they just cherry pick the best parts and have professional over clockers with LN hit these marks. It is largely unattainable by the average consumer to achieve this. But what about people who really don't know much about components, they will just assume that GIGABYTE is the best.

Its like a motorcycle I bought, the pictures for the ad had the rider doing wheelies. But in fine little print it said not to do this that it could damage your motor. It is IMHO misleading.

 

[jimmysmitty]

And then DDR4 launches and a few years after that this may be your average ram frequency.

DDR4 should go up to 4266 but it could also be like DDR3 which has surpassed its expected top end speed. Plus DDR4 will be hitting later this year with Haswell-E and probably Skylake at the latest for mainstream if not Broadwell so it is not too far off.

 

[InvalidError]

DDR4 should go up to 4266 but it could also be like DDR3 which has surpassed its expected top end speed.

The 4266MT/s high-end is an extrapolation from DDR3 managing to get somewhat decent yields at 2133 but the official spec does not go that high.

All DRAM interface generations have seen one or two speed grades beyond the highest standard speed grade in enthusiast kits. DDR3 is a bit odd in that regard with 4-5 pseudo-standard grades beyond JEDEC spec. DDR4 might not repeat that.

 

[TechyInAZ]

A Memory overclock like that would help A10-7850K to get a lot more FPS.

 

[ykki]

But the memory controller of the 7850k also has to keep up

 

[Someone Somewhere]

Should really change the title to MT/s...


And toss DDR3 in there; there's plenty of non-DDR3 that can go way above that. GDDR5 etc.

 

[InvalidError]

there's plenty of non-DDR3 that can go way above that. GDDR5 etc.

None of which is mounted on a DIMM nor connects to a socketed controller.

Part of the reason why GDDR3/5 can achieve 5-6GT/s is because there are no socket/slot interfaces between the DRAM dies and whatever ASIC they are connected to.

 

[Nuckles_56]

But can it play crysis?

 

[cream]

least we forget we have many cores that can run up to 4gb but getting over this barrier seems to have stalled going sideways in multi cores cpu this has stopped the cpu climb up that ladder least we forget has manufactures went this way sadly

 

[Drejeck]

It really doesn't matter the frequency you reach if you are loosening the latencies.
Having high IPCs is the most important thing because it's the real measure of memory quality. As an example A 2400 MHz CL9, like the GSkill 2x4 GTXD at 1,65V have 266,67 IPC, they can go to 2666 at CL10 or you can downclock them and still get 266 IPC to feed your system. MHz have been increasingly taking the spotlight because they ultimately influence data transfer and gaming but with pure mathematics at work 266 IPC is the same as 1333 MHz CL5 or 400 MHz CL 1.5. The larger the memory chip the slower the latency will be. In DDR4 we are going to see the same IPCs but since they already know that no motherboard will ever have more than one memory bank per channel they are doubling the density, slowing down latencies, and trying to recover with higher frequencies. The ram will cost less, if someone doesn't burn down or flood the factories, consume less, and probably processor will get advantage of the larger data transfer. The downside is that the memory bank will be really populated and low profile memories could disappear. If today 8GB is the minimum and 16GB is very popular, tomorrow 16GB could be a one bank memory, easily enabling people with two channels to have 32GB of ram and 64GB those with four channels. Ramdisks everywhere.

 

[InvalidError]

It really doesn't matter the frequency you reach if you are loosening the latencies.
Having high IPCs is the most important thing because it's the real measure of memory quality. As an example A 2400 MHz CL9, like the GSkill 2x4 GTXD at 1,65V have 266,67 IPC, they can go to 2666 at CL10 or you can downclock them and still get 266 IPC to feed your system.

That is some gross misunderstanding of how memory works you got going there. The latency is only the delay from command-in to data-in/out and you can interleave commands between memory banks and DIMMs to keep the data bus busy transferring data while waiting for another bank to get ready to send its data. There are also additional commands to open and close memory rows that get interleaved in the mix. A DDR3 memory controller can easily have 4-6 operations in-flight spread across the 8-32 memory banks connected to it.

The number of memory operations per second is far more complex (and higher) than just clock divided by CAS latency.

 

[Drejeck]

It really doesn't matter the frequency you reach if you are loosening the latencies.
Having high IPCs is the most important thing because it's the real measure of memory quality. As an example A 2400 MHz CL9, like the GSkill 2x4 GTXD at 1,65V have 266,67 IPC, they can go to 2666 at CL10 or you can downclock them and still get 266 IPC to feed your system.

That is some gross misunderstanding of how memory works you got going there. The latency is only the delay from command-in to data-in/out and you can interleave commands between memory banks and DIMMs to keep the data bus busy transferring data while waiting for another bank to get ready to send its data. There are also additional commands to open and close memory rows that get interleaved in the mix. A DDR3 memory controller can easily have 4-6 operations in-flight spread across the 8-32 memory banks connected to it.

The number of memory operations per second is far more complex (and higher) than just clock divided by CAS latency.

You're right, my bad, something confused me. I wanted to point out that we are not going to brake the 7ns first word access since DDR2 1066 CL 4.
Sorry for the disinformation. You may want to use that number as an index of quality, though, and use it to calculate compatible overclock/downclock with the right latency. DDR3 2400 CL9 sports a 7.5ns first word access.

 

[InvalidError]

I wanted to point out that we are not going to brake the 7ns first word access since DDR2 1066 CL 4.
Sorry for the disinformation. You may want to use that number as an index of quality, though, and use it to calculate compatible overclock/downclock with the right latency. DDR3 2400 CL9 sports a 7.5ns first word access.

While first-word latency has its use, it hardly is the be-all, end-all of memory performance metrics since the memory subsystem works on a cache-line basis and the CPU will often need more than only the first word.

Some highly non-linear algorithms like parsing code/html benefit more from lower latency but others like encoding, image processing, signal processing, IGPs, etc. benefit more from faster overall memory transaction completion time.

 

[illLoGiQ]

Yeah that's cool and all but what do them clocks on air look like? Last i checked it's still not common to tell the wife "Hey hun, I'm stepping out for some milk and LN"