News New UCIe Chiplet Standard Supported by Intel, AMD, and Arm

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Intel, AMD, Arm, TSMC, and Samsung, among others, introduced the new Universal Chiplet Interconnect Express (UCIe) consortium to standardize die-to-die interconnects between chiplets with an open-source design, thus reducing costs and fostering a broader ecosystem of valid parts.

New UCIe Chiplet Standard Supported by Intel, AMD, and Arm : Read more

 

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this stuff sounds interesting but way over my head. what exactly is a chiplet, how do they impact stuff for consumer or server level hardware?

my understanding is that this is part of a move from general purpose CPUs to specialized chips for lots of little things - like say matrix multiplies for AI or video decoders or crypto miners. this common standard would let different players specialize in different sorts of chiplets and bundle it all into one chip that say a consumer building their own PC or a mobile phone manufacturer could buy. is that sort of in the right ballpark?

 

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my understanding is that this is part of a move from general purpose CPUs to specialized chips for lots of little things

Chiplet/tile designs have three key benefits:

1. by breaking down large chip design into multiple smaller parts, each part can be tested separately to reduce the amount of wafer space lost on fill factor (you can fill a wafer closer to the edge with smaller dies) and the amount of space lost on dies with fatal defects on them
2. you can mix-and-match processes to use the best process available for things that generally cannot be done on one single chip without massive compromises, ex.: DRAM requires a low-leakage process that produces transistors too slow for high-speed logic, chiplets lets you bring the two processes together in one design and
3. you can create a whole product range out of semi-standard legos, which could possibly include more semi-custom options like what you mentioned.

The downside is that chip-to-chip interconnects do add chip manufacturing complexity, latency and consume more die area than monolithic, especially when you add standardized protocol layers in-between. So as far as CPU designs are concerned, I doubt they will be breaking those down smaller than compute clusters sharing their local L3 cache like AMD has been doing with Zen 2/3.

 

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Chiplet/tile designs have three key benefits:

1. by breaking down large chip design into multiple smaller parts, each part can be tested separately to reduce the amount of wafer space lost on fill factor (you can fill a wafer closer to the edge with smaller dies) and the amount of space lost on dies with fatal defects on them
2. you can mix-and-match processes to use the best process available for things that generally cannot be done on one single chip without massive compromises, ex.: DRAM requires a low-leakage process that produces transistors too slow for high-speed logic, chiplets lets you bring the two processes together in one design and
3. you can create a whole product range out of semi-standard legos, which could possibly include more semi-custom options like what you mentioned.

The downside is that chip-to-chip interconnects do add chip manufacturing complexity, latency and consume more die area than monolithic, especially when you add standardized protocol layers in-between. So as far as CPU designs are concerned, I doubt they will be breaking those down smaller than compute clusters sharing their local L3 cache like AMD has been doing with Zen 2/3.

Oh okay, so it sounds like the purpose of these designs is about better internal manufacturing efficiencies and not necessarily something that translates directly into a consumer visible change beyond price then. Thanks i appreciate the answer.

 

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Oh okay, so it sounds like the purpose of these designs is about better internal manufacturing efficiencies and not necessarily something that translates directly into a consumer visible change beyond price then. Thanks i appreciate the answer.

And you could add:
4) (as a corollary to #1) with defects limited to smaller pieces of silicon eliminating the high risk of massive monolithic designs especially on cutting-edge processes, it also enables the fabrication of multi-die monstrosities like Ponte Vecchio (40+ active tiles) and whatever even more ambitious projects are likely to follow.