You are probably right about the 4.5 GHz, but the rule of thumb is too crude. Nowadays I think the advancement of clock speed depends heavily on:
1. Design. With the same 0.18 micron technology, PIII could not go beyond 1 GHz, but P4 could scale 1.7 GHz. It is because the new 21-stage pipeline design makes the differences. Of course, we know clock speed does not necessarily mean performance when there is a trade-off between clock speed and efficiency.
2. Heat management. Shorter channel length allows comparable drive current with lower supply voltage, which is the key to high clock speed since for a given chip, power goes with fV^2, where f is the clock speed and V is the supply voltage. Without a significant reduction of V, ultra high clock speed would be impossible (at least for air cool).
3. Reliability. However, in order to scale the transistors the gate oxide needs to be reduced as well. When the gate oxide gets too thin, the leakage and reliability become show stoppers. For example, Intel is using ~1.5 nm thick (about 5 mono-layers) silicon oxide for its 0.13 micron technology. Since no one can afford to run thousands of devices for 5 years to come up precise reliability data, everyone has been counting on accelerated aging tests (higher current and temperature) to predict reliability. Well, it is pretty controversial about how reliable such a think gate oxide can be and how much the accelerated tests can tell us at this point. Companies such as Intel basically charge ahead without a consensus from the industry. I can appreciate that they may not have a choice because of severe competition, but we will see what happen to those devices in a year or two.
**Spin all you want, but we the paying consumers will have the final word**
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