- Jan 29, 2001
- 8,713
- 4
- 31,815
This is a long post, cause I need a lot of advice.
My system is:
Pentium II 300MHz (KLAMATH)
Aopen AX6L Mobo
256MB (2x128) 100MHz SDRAM
AGP slot (32MB ATI Rage Fury) AGP aperture size set at 128MB
PCI slots with Rockwell 56k modem & Adaptec SCSI card (ZIP 100)
ISA slot with Creative Sound Blaster AWE64
Everthing else is standard.
I need to know abpout the following BIOS stuff. I downloaded the specs from Aopen, but you need to know what it means in the first place to understand them. I have marked the current setting in each case. Can anyone tell me if this is the right settings for my system. I may want to try overclocking, since it is a jumperless system, so any advice on that is great too.
BIOS Features C800-CBFF Shadow
BIOS Features CC00-CFFF Shadow
BIOS Features D000-D3FF Shadow
BIOS Features D400-D7FF Shadow
BIOS Features D800-DBFF Shadow
BIOS Features DC00-DFFF Shadow
C8000-CBFFF Shadow
Enabled
Disabled*
These six items are for shadowing ROM code on other expansion cards. Before you set these parameters, you need to know the specific addresses of that ROM code. If you do not know this information, enable all the ROM shadow settings.
Note: The F000 and E000 segments are always shadowed because BIOS code occupies these areas.
EDO RAS# to CAS# Delay
2*
3
This option allows you to set the wait state between row address strobe (RAS) and column address strobe (CAS) signals.
EDO RAS# Precharge Time
3*
4
This parameter specifies the number of clocks required to deassert the RAS signal to prevent DRAM from losing data after performing a read. This operation is called Precharge.
EDO DRAM Read Burst
x333
x222*
Read Burst means to read four continuous memory cycles on four predefined addresses from the DRAM.The default value is x222 for 60ns EDO DRAM. Which means the 2nd,3rd and 4th memory cycles are 2 CPUclocks for EDO. The value of x is the timing of first memory cycle.
EDO DRAM Write
Burst
x333
x222*
Write Burst means to write four continuous memory cycles on four predefined addresses to the DRAM. The default value is x222 for 60ns EDO DRAM. Which means the 2nd,3rd and 4th memory cycles are 2 CPU clocks for EDO. The value of x is the timing of first memory cycle.
SDRAM(CAS Lat/RAS-to-CAS)
2/2
3/3*
These are timing of SDRAM CAS Latency and RAS to CAS Delay, calculated by clocks. They are important parameters affects SDRAM performance, default is 2 clocks. If your SDRAM has unstable problem, change 2/2 to 3/3.
SDRAM RAS Precharge Time
2T
3T*
The RAS Precharge means the timing to inactive RAS and the timing for DRAM to do precharge before next RAS can be issued. RAS is the address latch control signal of DRAM row address. The default setting is 3 clocks.
DRAM Loading
Normal*
Heavy
When you find the system unstable, check the DRAM chip count. If the chip count is more than 64, set this option to Heavy.
Tip: 64 is only for your reference. Sometimes you may try to set this option to Heavy as long as the chip count is large.
Tip: The driving capability of new generation chipset is limited because the lack of memory buffer (to improve performance).
This makes DRAM chip count an important factor to be taking into consideration when you install DIMM. Unfortunately, there is no way that BIOS can identified the correct chip count, you need to calculate the chip count by yourself.
The simple rule is: By visual inspection, use only DIMM which is less than 16 chips.
DRAM ECC Function
Enabled
Disabled*
This item lets you enable or disable DRAM ECC function. The ECC algorithm has the ability to detect double bit error and automatically correct single bit error.
Video BIOS Cacheable
Enabled
Disabled*
Allows the video BIOS to be cached to allow faster video performance.
Video RAM Cacheable
Enabled
Disabled*
This item lets you cache Video RAM A000 and B000.
8 Bit I/O Recovery Time
1
2
3
4*
5
6
7
8
NA
For some old I/O chips, after the execution of an I/O command, the device requires a certain amount of time (recovery time) before the execution of the next I/O command. Because of new generation CPU and mainboard chipset, the assertion of I/O command is faster, and sometimes shorter than specified I/O recovery time of old I/O devices. This item lets you specify the delay of 8-bit I/O command by count of ISA bus clock. If you find any unstable 8-bit I/O card, you may try to extend the I/O recovery time via this item. The BIOS default value is 4 ISA clock. If set to NA, the chipset will insert 3.5 system clocks.
16 Bit I/O Recovery
Time
1*
2
3
4
NA
The same as 16-bit I/O recovery time. This item lets you specify the recovery time for the execution of 16-bit I/O commands by count of ISA bus clock. If you find any of the installed 16-bit I/O cards unstable, try extending the I/O recovery time via this item. The BIOS default value is 1 ISA clocks. If set to NA, the chipset will automatically insert 3.5 system clocks.
Memory Hole At 15M-16M
Enabled
Disabled*
This option lets you reserve system memory area for special ISA cards. The chipset accesses code/data of these areas from the ISA bus directly. Normally, these areas are reserved for memory mapped I/O card.
Passive Release
Enabled
Disabled*
This item lets you control the Passive Release function of the PIIX4 chipset (Intel PCI to ISA bridge). This function is used to meet latency of ISA bus master. Try to enable or disable it, if you have ISA card compatibility problem.
Delayed Transaction
Enabled
Disabled*
This item lets you control the Delayed Transaction function of the PIIX4 chipset (Intel PCI to ISA bridge). This function is used to meet latency of PCI cycles to or from ISA bus. Try to enable or disable it, if you have ISA card compatibility problem.
Finally, until I get the money together for my next system, I'd consider a CPU upgrade. I don't want to upgrade this system in any other way. What can I do. Is a slot1 - socket 370 converter a good idea.
Thanks in advance to any help given. I'll never write a post like this again.
The End.
My system is:
Pentium II 300MHz (KLAMATH)
Aopen AX6L Mobo
256MB (2x128) 100MHz SDRAM
AGP slot (32MB ATI Rage Fury) AGP aperture size set at 128MB
PCI slots with Rockwell 56k modem & Adaptec SCSI card (ZIP 100)
ISA slot with Creative Sound Blaster AWE64
Everthing else is standard.
I need to know abpout the following BIOS stuff. I downloaded the specs from Aopen, but you need to know what it means in the first place to understand them. I have marked the current setting in each case. Can anyone tell me if this is the right settings for my system. I may want to try overclocking, since it is a jumperless system, so any advice on that is great too.
BIOS Features C800-CBFF Shadow
BIOS Features CC00-CFFF Shadow
BIOS Features D000-D3FF Shadow
BIOS Features D400-D7FF Shadow
BIOS Features D800-DBFF Shadow
BIOS Features DC00-DFFF Shadow
C8000-CBFFF Shadow
Enabled
Disabled*
These six items are for shadowing ROM code on other expansion cards. Before you set these parameters, you need to know the specific addresses of that ROM code. If you do not know this information, enable all the ROM shadow settings.
Note: The F000 and E000 segments are always shadowed because BIOS code occupies these areas.
EDO RAS# to CAS# Delay
2*
3
This option allows you to set the wait state between row address strobe (RAS) and column address strobe (CAS) signals.
EDO RAS# Precharge Time
3*
4
This parameter specifies the number of clocks required to deassert the RAS signal to prevent DRAM from losing data after performing a read. This operation is called Precharge.
EDO DRAM Read Burst
x333
x222*
Read Burst means to read four continuous memory cycles on four predefined addresses from the DRAM.The default value is x222 for 60ns EDO DRAM. Which means the 2nd,3rd and 4th memory cycles are 2 CPUclocks for EDO. The value of x is the timing of first memory cycle.
EDO DRAM Write
Burst
x333
x222*
Write Burst means to write four continuous memory cycles on four predefined addresses to the DRAM. The default value is x222 for 60ns EDO DRAM. Which means the 2nd,3rd and 4th memory cycles are 2 CPU clocks for EDO. The value of x is the timing of first memory cycle.
SDRAM(CAS Lat/RAS-to-CAS)
2/2
3/3*
These are timing of SDRAM CAS Latency and RAS to CAS Delay, calculated by clocks. They are important parameters affects SDRAM performance, default is 2 clocks. If your SDRAM has unstable problem, change 2/2 to 3/3.
SDRAM RAS Precharge Time
2T
3T*
The RAS Precharge means the timing to inactive RAS and the timing for DRAM to do precharge before next RAS can be issued. RAS is the address latch control signal of DRAM row address. The default setting is 3 clocks.
DRAM Loading
Normal*
Heavy
When you find the system unstable, check the DRAM chip count. If the chip count is more than 64, set this option to Heavy.
Tip: 64 is only for your reference. Sometimes you may try to set this option to Heavy as long as the chip count is large.
Tip: The driving capability of new generation chipset is limited because the lack of memory buffer (to improve performance).
This makes DRAM chip count an important factor to be taking into consideration when you install DIMM. Unfortunately, there is no way that BIOS can identified the correct chip count, you need to calculate the chip count by yourself.
The simple rule is: By visual inspection, use only DIMM which is less than 16 chips.
DRAM ECC Function
Enabled
Disabled*
This item lets you enable or disable DRAM ECC function. The ECC algorithm has the ability to detect double bit error and automatically correct single bit error.
Video BIOS Cacheable
Enabled
Disabled*
Allows the video BIOS to be cached to allow faster video performance.
Video RAM Cacheable
Enabled
Disabled*
This item lets you cache Video RAM A000 and B000.
8 Bit I/O Recovery Time
1
2
3
4*
5
6
7
8
NA
For some old I/O chips, after the execution of an I/O command, the device requires a certain amount of time (recovery time) before the execution of the next I/O command. Because of new generation CPU and mainboard chipset, the assertion of I/O command is faster, and sometimes shorter than specified I/O recovery time of old I/O devices. This item lets you specify the delay of 8-bit I/O command by count of ISA bus clock. If you find any unstable 8-bit I/O card, you may try to extend the I/O recovery time via this item. The BIOS default value is 4 ISA clock. If set to NA, the chipset will insert 3.5 system clocks.
16 Bit I/O Recovery
Time
1*
2
3
4
NA
The same as 16-bit I/O recovery time. This item lets you specify the recovery time for the execution of 16-bit I/O commands by count of ISA bus clock. If you find any of the installed 16-bit I/O cards unstable, try extending the I/O recovery time via this item. The BIOS default value is 1 ISA clocks. If set to NA, the chipset will automatically insert 3.5 system clocks.
Memory Hole At 15M-16M
Enabled
Disabled*
This option lets you reserve system memory area for special ISA cards. The chipset accesses code/data of these areas from the ISA bus directly. Normally, these areas are reserved for memory mapped I/O card.
Passive Release
Enabled
Disabled*
This item lets you control the Passive Release function of the PIIX4 chipset (Intel PCI to ISA bridge). This function is used to meet latency of ISA bus master. Try to enable or disable it, if you have ISA card compatibility problem.
Delayed Transaction
Enabled
Disabled*
This item lets you control the Delayed Transaction function of the PIIX4 chipset (Intel PCI to ISA bridge). This function is used to meet latency of PCI cycles to or from ISA bus. Try to enable or disable it, if you have ISA card compatibility problem.
Finally, until I get the money together for my next system, I'd consider a CPU upgrade. I don't want to upgrade this system in any other way. What can I do. Is a slot1 - socket 370 converter a good idea.
Thanks in advance to any help given. I'll never write a post like this again.
The End.
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