PCIe 5.0 Coming In 2019; PCI-SIG Fast Tracks Final Spec

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Nothing prevents AMD from upgrading AM4's existing PCIe lanes to PCIe 4.0/5.0 in future CPUs and 3.0/4.0 in future chipsets, though you'll need a new motherboard if you want to use the updated chipsets' faster PCIe and may need it for the CPU lanes too if your pre-4.0/5.0 motherboard's CPU PCIe lanes don't meet specs.
 

Yeah that's the sort of thing they've done before with "+" platform refreshes. I think they'll eventually release an AM4+ refresh. If that happens I would aldo bet most existing boards will work with the new CPUs with a BIOS update, but potentially without PCIe 4.0. Meanwhile newer boards will run older AM4 CPUs, but will absolutely lack PCIe 4.0 in that situation.

This has worked well for them in the past. On the consumer side of things PCIe 4.0 and beyond won't be a big deal for the next couple of years, in particular for the majority of people using a single graphics card with a 16 lane slot. With that being said, I don't want them to wait TOO long. PCIe 5.0 might require a new platform though... thoughts?
 
@ chriz78

Quote, "Expect RJ-45 400GigE to be right around the corner!"

Nope, not around any corner I can yet see, and I'm still deploying 100G channels like crazy. But as I gear up for upcoming 400G deployments, you should know you'll not be seeing that on an RJ45 any time soon, if ever.

400G uses the CFP8 form factor, which physicall is about the size of CFP2 that is becoming ubiquitious, and optically, its 4x100G (mostly) on a single fiber, or 1x400G (rare), plus a couple of other number of waves & bit rates.

But the real info is that electrically, it is 16x 25Gb/s bit rate on the electrical connector. I can't wait to see a picture of your motherboard with 16x25Gb/s electrical interfaces.
 


It won't be RJ45 as it already has issues with crosstalk and too thin wires. It would be far better to go away from wires and go optical as you won't have issues with interference or crosstalk. And at those speeds you don't want any interruptions in the traffic. RJ45 is still around only because it's such a standard and it works for the majority of the nets, but even at 10Gbit you rather go fiber as it's more reliable. Only when doing PoE is it required (obviously) to go with copper. And regardless the cost of 400GigE will be far outside of regular consumer wallets. Only recently has 10Gbe become affordable for end users and it's been around since 2002.
 
Expect RJ-45 400GigE to be right around the corner! :pt1cable:

Sorry, I guess my sarcasm was not very obvious. Considering 10gigE has been out for how long? Anyway, it's been many years, and still not affordable. So ethernet reaching 400Gb/s means absolutely nothing to me.
 

On the CPU-hosted lanes side of things, it should require little more than PCIe traces and AM4 sockets with ~4X tighter electrical parameters tolerances.
 

Look at any motherboard with a x16 PCIe slot, that's what it'll look like in add-in-board format. Simply plug your 400GbE card into a PCIe 5.0 x16 slot, done. For on-board networking, it gets much simpler since you don't need to maintain ground plane integrity through a card edge connector.
 
Can we at least have PCIe 4.0 shipping in actual mobos and video cards first, please.
Thath thing has been dragged on for years now and there is still NO guarantee that we'll see. PCIe 4.0 mobos and gfx cards even next year. Interconnect chips sure, but if Intel/AMD/nVidia drag their feet, then no way do we see itnin 2018.
 
Paper launch of course. We are still using PCIE 3.0. AMD just got PCIE 3.0 this year. Unless they are going to skip 4 and go straight to 5, I doubt this will be on any consumer mobo/CPU for several years.
 

Until NVMe came along, there were effectively no consumer devices capable of making use of this much bandwidth. Now, with 3D-NAND/XPOINT gaining popularity, there will be plenty of demand for interfaces capable of 16+Gbps per lane in the not-too-distant future and IO needs to catch up.

PCIe 4.0 simply happened to get released during a time where nobody had much of a motivation to look at faster IO. Now, 4.0 is too little too late and we get 5.0 instead.
 
Don't get too excited just yet. It will be a good five years or more before this appears in the consumer sector. There is still a lot to be done with PCIe 4.0 bringing NVMe devices into the mainstream. Being able to get 3.0 performance with half the lanes with bring the price down on stuff once 4.0 itself becomes the mainstream standard. Around that time the OSes should have a better handle at exploiting the performance. The recently leaked high-end workstation SKU for Windows should be where this stuff gets refined before being exposed to ordinary consumers.
 

I took that comment to be ironic. We can safely say that there'll never be a 400 Gbps ethernet over RJ-45.


Heh, like IE said... did you already lose context? This thread is ostensibly about PCIe 5.0. 100 Gb ethernet NICs are currently available as PCIe 3.0 x16 add-in cards. Not content to wait around for PCIe 4.0, Intel is integrating 200 Gbps OmniPath directly into some of their new Xeon CPUs.

So, with Nvidia/IBM going for NVLink and Intel going for OmniPath, I guess that just leaves AMD holding the mantle of standards-based products. And what do they get for it? A 4000+ pin socket. That's one thing. And I thought Purley was huge...
 

AMD uses Infinity Fabric (souped-up HyperTransport) between CPU dies and sockets, not quite standard there either.
 

First, that runs over PCIe. So, to the extent possible, I think it is standards-based. Honestly, what else would you have them use?

Second, apples & oranges. What I'm talking about is how their CPUs interact with other devices, such as GPUs and networking. It's not a minor point. Intel is trying to force customers to use their OmniPath networking, and IBM is trying to force customers to use Nvidia GPUs.
 

Talk of apples and oranges... Intel's OmniPath adapters run over PCIe 3.0 and they are the successor to InfiniBand and TrueScale. They aren't replacements for regular networking.
 
Doubling of the speed is like doubling of the lanes but with less space/wires.

Sad that AMD isn't moving on this, sad that Intel wasn't on this already.
 
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