News PCIe 6.0 over optical cables demonstrated in custom data center solution

[Admin]

Nubis Communications and Alphawave Semi demonstrate PCIe 6.0 interconnection over optical cables.

PCIe 6.0 over optical cables demonstrated in custom data center solution : Read more

 

[KraakBal]

The title says x16 but the article says x8. Does the reporter even know what pcie is?

 

[bit_user]

The title says x16 but the article says x8.

The article says "x8 per fiber", which implies two fibers are needed for a x16 link.

It goes on to say:

"Our high level of integration with 16 lanes full-duplex in a single low-power, low-latency optical engine ... "
​

So, it sounds like they indeed do do have a full x16 lane solution.

Does the reporter even know what pcie is?

Very much.

 

[bit_user]

What I wonder is whether we can anticipate such high-speed optical being routed through PCBs, or will it always require optical cables?

 

[strobolt]

What I wonder is whether we can anticipate such high-speed optical being routed through PCBs, or will it always require optical cables?

I would believe so (based on no real information).

My reasoning is that it would just require thicker copper on the PCB to enable that. In the article they were also saying that optical enables greater lengths *without* sacrificing bandwidth. I'm reading that as the the copper wouldn't yet be at its maximum bandwidth (in theoretical physical terms, if such exist) and the problem is mostly about controllers, use cases and costs that prohibit implementation on consumer grade products.

 

[bit_user]

I would believe so (based on no real information).

My reasoning is that it would just require thicker copper on the PCB to enable that.

So, that's not at all what I meant. I wanted to know if you could put glass traces in a PCB and route such high-speed optical links through it.

In the article they were also saying that optical enables greater lengths *without* sacrificing bandwidth. I'm reading that as the the copper wouldn't yet be at its maximum bandwidth (in theoretical physical terms, if such exist) and the problem is mostly about controllers, use cases and costs that prohibit implementation on consumer grade products.

I'm not an electrical engineer, but I've been following the development of PCIe pretty closely. They apparently had such issues with bandwidth beyond PCIe 5.0 that, instead of doubling the frequency for 6.0, they used PAM4. That's not a free lunch, either, because it requires a better signal-to-noise ratio. That, in turn, will tend to require more expensive motherboards with more layers, in order to reduce interference. And this is already presuming you have retimers, I'm pretty sure (since they seem to be somewhat ubiquitous).

We haven't even talked about power, but that's another issue with trying to push ever higher frequencies over copper. AMD has stated that embracing optical interconnects will become a necessity for continuing to scale performance, over the next decade. Otherwise, the poor efficiency of scaling copper links would eat up too much of your power budget.

 

[TJ Hooker]

The article says "x8 per fiber", which implies two fibers are needed for a x16 link.

Neither this article nor the source press release contain the quote "x8 per fiber", they refer to a "PCIe 6.0 x8 link". The only per fiber metric they mention is "64GT/s per fiber", which is just the per-lane bit rate of PCIe 6.0.

It goes on to say:

"Our high level of integration with 16 lanes full-duplex in a single low-power, low-latency optical engine ... "
So, it sounds like they indeed do do have a full x16 lane solution.

Yeah, this explanation does seem the most likely, i.e. they're touting a solution beyond what was presented here. I do think the way they presented it is sort of confusing though. Like 'by demonstrating an x8 PCIe link, we show we can support a x16 PCIe link!' If it's easy to scale their technology up to a x16 link, why not use that for the demo?

 

[bit_user]

Neither this article nor the source press release contain the quote "x8 per fiber", they refer to a "PCIe 6.0 x8 link". The only per fiber metric they mention is "64GT/s per fiber", which is just the per-lane bit rate of PCIe 6.0.

I was paraphrasing, in order to simply and clearly relate it to what the poster said.

Okay, so the entire quote is

"This setup achieves PCIe 6.0 x8 optical link at 64 GT/s per fiber, without retimers."
​

Upon rereading, I see that the lack of commas makes it somewhat ambiguous exactly what's being said.

The original press release says:

“Our high level of integration with 16 lanes full-duplex in a single low-power, low-latency optical engine is a great match to the maximum bandwidth of PCIe x16 for next-generation compute and storage deployments,” said Scott Schube, VP of Marketing at Nubis Communications. “Our demonstration of the Nubis XT1600 linear optical engine and Alphawave Semi’s PCIe 6.0 Controller and PHY IP showcases the viability of a PCIe® 6.0 x8 link over optical fiber at 64 GT/s.”
​

Okay, so I read that as saying:

1. Their solution is designed to handle PCIe 6.0 x16 with a single optical engine.
2. They demonstrated it running at x8.

Yeah, this explanation does seem the most likely, i.e. they're touting a solution beyond what was presented here. I do think the way they presented it is sort of confusing though. Like 'by demonstrating an x8 PCIe link, we show we can support a x16 PCIe link!' If it's easy to scale their technology up to a x16 link, why not use that for the demo?

I agree with you on all points. My guess about why they only demo'd it at x8 is either due to the complexity of prototyping at x16 or maybe due to some bug or issue they expect to be resolved in the final product. Or, perhaps they lacked some infrastructure needed to demo it at full x16?

In any case, I think it's not a bad snapshot of the current tech. For folks like us, that's enough.