News PCIe 6.0 Ready for Chip Designs: Synopsys Unveils Complete PCI Express 6.0 Solution

[Admin]

Synopsys has DesignWare controller, physical interface, and verification IP for 5nm chips.

PCIe 6.0 Ready for Chip Designs: Synopsys Unveils Complete PCI Express 6.0 Solution : Read more

 

[Jim90]

As always, most excellent to see progress!
Would be equally excellent, though, to see the inevitable bottlenecks being tackled at the same time - everything else in that connected chain would keep up, in an ideal world.

 

[samopa]

So, can we just skip PCIE 5.0 entirely and directly implement PCIE 6.0 ?

 

[InvalidError]

So, can we just skip PCIE 5.0 entirely and directly implement PCIE 6.0 ?

Sure, skip to 6.0 when 4.0 is already considerably more power-hungry than 3.0 so we can have chipsets that require tower coolers and CPUs that require multiple VRM phases dedicated to bus power

I'm ok with waiting for that stuff to get cheaper and more power-efficient.