If they continue having a separate I/O die, then desktop CPUs won't just inherit PCIe 5.0+ "for free".I wonder if it's more convenient to just have their CPUs "PCIe 6.0 ready" but on motherboards, split the bandwidth across more PCIe 5.0 or even PCIe 4.0 lanes.
72GB/s for GDDR6? For a RX5700XT that's 16GT/s x 256bits = 512GB/s.So is it possible to have proper SLI or Crossfire with pcie 6.0 without any bridge since GDDR6 bandwidth is 72 GBps and pcie 6.0 bandwidth is 128 GBps.
FWIW, I guess AMD is using lower-clocked GDDR6 than wherever that 72 GB/s is from, because the rated spec of RX 5700XT is 448 GB/sec. That detail aside, I agree with your basic point, which seems to be that one needs to look at the bandwidth for the whole GPU.72GB/s for GDDR6? For a RX5700XT that's 16GT/s x 256bits = 512GB/s.
Yeah, I think latency is a killer. That is, if you want to use multiple GPUs to reach really high frame rates.If you want to make multiple GPUs behave like a single larger one, you'll need even more bandwidth and lower latency than that to account for all of the other internal processes that require bandwidth too but never have to leave the die in single-GPU setups.
Using AMD as an example; I meant something like a theoretical "6000" or "7000" series Ryzen/TR CPU having PCIe 6.0 on-die, but motherboards outside of specialized Enterprise/Commercial downgrading that to PCIe 5.0 or even 4.0 bandwidth to allow for more slots while still providing some future-proofing via future motherboards (easier on AMD with socket sharing over 3-4 chipset generations, questionable on Intel).If they continue having a separate I/O die, then desktop CPUs won't just inherit PCIe 5.0+ "for free".
As you rightly point out, faster interconnect speeds is a costly proposition. I don't see it coming to desktops, though it'd be interesting if they upgraded the CPU <-> chipset with a PCIe 5.0 or PCIe 6.0 link. As you point out, that could enable more/wider/faster chipset-connected slots.
5.0 needs retimers. As I'm not an electronics engineer, I can't comment on the potential for cost reductions, but they'll never cost as little as not having any.Especially since by the time PCIe 6.0 becomes an actual adopted thing, 4.0 and 5.0 signal repeaters will likely have come down in costs some due to aggressive adoption by AMD and Intel down to the consumer level
You mean like room temperature superconductors? That would indeed be a game changer.or advances in material design would be advanced enough allowing for boards not needing as many (or not needing any) repeaters for 4.0 or 5.0 traces
The only possibility I'm seriously entertaining is PCIe 5.0 between the CPU and chipset, and only because the chipset is soldered and can be located near the CPU. Perhaps 6.0 could eventually follow, if there's a sufficient need to justify the additional complexity and power consumption.On the middle/mainstream end of motherboards (B-series on AMD), we could maybe even see an on-die PCIe 6.0 downgraded further to mostly PCIe 3.0, for all slots except the 1st M.2 and GPU slot. So maybe PCIe 4.0 M.2 and x16 slot, and the remainder x16 or x8 full-length PCIe 3.0 slots.
This should come in very handy... in about 2028....The PCIe 6.0 spec doubles the data rate of the last generation.
PCIe 6.0 Spec Release Date on Track, Version 0.5 Announced : Read more
That would be quite the feat. Given that it would be an order of magnitude smaller than a hydrogen atom. Which has a radius between 0.025 and 0.086 nm.And just like 386DX was originally manufactured on a 1500 nm process node, I predict that we'll be able to fab chips at 0.0035 nm.
Due to the signal integrity challenges of pushing 50+Gbps over consumer-friendly PCB materials, my bet is that the consumer space will go with optical plug-in interconnects first. If PCIe 6.0 makes it to consumer boards, I doubt it'll go beyond chips soldered to the motherboard like the chipset.Just as a 386DX was "for server rooms only"...this too shall eventually trickle down to the consumer space.
For sure. I was simply trying to illustrate that every trend breaks down.That would be quite the feat. Given that it would be an order of magnitude smaller than a hydrogen atom. Which has a radius between 0.025 and 0.086 nm.