Playstation 4 DDR5 myth

[Roberto77]

I'm getting pretty tired of the Sony fanboys bleating that only the PS4 is truly next gen because it has 8GB of GDDR5 RAM and PC's will never match this, become obsolete... ect. ect.

From my understanding GDDR5 is based on the same chips as DDR3 with a different fetch, clock and timing arrangement designed for extremely high burst speeds for the serial highly parallel access that A GPU generates, and the reason it isn't used for system, ram is that the increased latency would actually hurt performance on a CPU.

Wondered if anyone can offer a more educated opinion on this.

 

[DarkSable]

They don't know what they're talking about.

G(raphics)DDR5 is used in most high-end video cards today - the Titan has 6GB of GDDR5.

The ONLY thing GDDR is used for is as a frame buffer; that is, it stores the rendered image before it gets sent to the monitor.

I haven't heard anyone 'bleating' about this, but if they are, they're bragging over something that doesn't do much of anything, and certainly isn't "next gen" - PCs have had GDDR 5 video cards since 2008. (The only reason that Sony put so much in there is so they have a high enough memory buffer that Sony fanboys can use their overpriced console with their overpriced Sony 4k TV.)

 

[groundrat]

Like its predecessor, GDDR4, GDDR5 is based on DDR3 SDRAM memory which has double the data lines compared to DDR2 SDRAM, but GDDR5 also has 8-bit wide prefetch buffers similar to GDDR4.

GDDR5 SGRAM conforms to the standards which were set out in the GDDR5 specification by the JEDEC. It uses an 8n-prefetch architecture and DDR interface to achieve high performance operation and can be configured to operate in ×32 mode or ×16 (clamshell) mode which is detected during device initialization. The GDDR5 interface transfers two 32-bit wide data words per write clock (WCK) cycle to/from the I/O pins. Corresponding to the 8n-prefetch, a single write or read access consists of a 256-bit wide two CK clock cycle data transfer at the internal memory core and eight corresponding 32-bit wide one-half WCK clock cycle data transfers at the I/O pins.

GDDR5 operates with two different clock types. A differential command clock (CK) as a reference for address and command inputs, and a forwarded differential write clock (WCK) as a reference for data reads and writes. Being more precise, the GDDR5 SGRAM uses two write clocks, each of them assigned to two bytes. The WCK runs at twice the CK frequency. Taking a GDDR5 with 5 Gbit/s data rate per pin as an example, the CK clock runs with 1.25 GHz and WCK with 2.5 GHz. The CK and WCK clocks will be aligned during the initialization and training sequence. This alignment allows read and write access with minimum latency.

As to why it is not used for main system memory, the 256 bit wide data cycle and the accompanying latency problems would most likely overwhelm a 64 bit processor.

 

[Roberto77]

Good info, tells me something interesting then, GDDR's bus is wider, four times so to be precise, but since the PS4's CPU is a fairly standard 64 bit AMD APU I suspect that it will never be able to take advantage of that bandwidth.

 

[groundrat]

Don't bet on that.
http://www.tomshardware.com/news/playstation-4-ps4-amd-apu-hardware,21191.html

The APU might be 64 bit, but its a customized 8 core and will no doubt be able to handle the data throughput. Link that to a GPU that operates at... wait for it... 1.84 TFLOPS and you have some fairly respectable hardware. Not a console fanboy, but with a RISC OS, it will definetly be able to throw frames.

 

[James Mauro]

Like its predecessor, GDDR4, GDDR5 is based on DDR3 SDRAM memory which has double the data lines compared to DDR2 SDRAM, but GDDR5 also has 8-bit wide prefetch buffers similar to GDDR4.

GDDR5 SGRAM conforms to the standards which were set out in the GDDR5 specification by the JEDEC. It uses an 8n-prefetch architecture and DDR interface to achieve high performance operation and can be configured to operate in ×32 mode or ×16 (clamshell) mode which is detected during device initialization. The GDDR5 interface transfers two 32-bit wide data words per write clock (WCK) cycle to/from the I/O pins. Corresponding to the 8n-prefetch, a single write or read access consists of a 256-bit wide two CK clock cycle data transfer at the internal memory core and eight corresponding 32-bit wide one-half WCK clock cycle data transfers at the I/O pins.

GDDR5 operates with two different clock types. A differential command clock (CK) as a reference for address and command inputs, and a forwarded differential write clock (WCK) as a reference for data reads and writes. Being more precise, the GDDR5 SGRAM uses two write clocks, each of them assigned to two bytes. The WCK runs at twice the CK frequency. Taking a GDDR5 with 5 Gbit/s data rate per pin as an example, the CK clock runs with 1.25 GHz and WCK with 2.5 GHz. The CK and WCK clocks will be aligned during the initialization and training sequence. This alignment allows read and write access with minimum latency.

As to why it is not used for main system memory, the 256 bit wide data cycle and the accompanying latency problems would most likely overwhelm a 64 bit processor.

But one is a read and the other is a write. DDR3 and DDR4 can only read or write.
If i was sony, i would have used that ability more than anything else. Which honestly should have removed any hesitation about the CAS long ago... Essentially if ddr3 memory does 1 thing (doubled)
Heres a real equation for timing in nano secounds

DDR3 (cas # / (MHZ# / 2)) * 1000 = time in nano seconds (ns)
DDR5 (cas # / (MHZ # *2)) * 1,000 = time in nano seconds (ns) the smaller number wins
---------------if i where sony i would have taken the advantage over the fact that DDR5 can read and write at the same time, while DDR3 can read or write but not in the same timing. And sense it is DDR5 with that huge bandwidth i think 176gbs where ddr3 of that size would (if your very lucky 20gbs) you would need significantly more ddr3 in your computer let alone the fact that DDR3 isn't very good for multitasking.

 

[James Mauro]

They don't know what they're talking about.

G(raphics)DDR5 is used in most high-end video cards today - the Titan has 6GB of GDDR5.

The ONLY thing GDDR is used for is as a frame buffer; that is, it stores the rendered image before it gets sent to the monitor.

I haven't heard anyone 'bleating' about this, but if they are, they're bragging over something that doesn't do much of anything, and certainly isn't "next gen" - PCs have had GDDR 5 video cards since 2008. (The only reason that Sony put so much in there is so they have a high enough memory buffer that Sony fanboys can use their overpriced console with their overpriced Sony 4k TV.)

Actually in the PS4 it is not just used for video cards like computer's it also doubles as cpu memory. There should be no lag in cpu.
DDR is double data rate,, basically TWO throughputs ddr3 is double DDR2 and so on
DRR4 is built on DDR 3 but it has 8bit wide channels instead of 2 bit
Whats so special about DDR5 you ask.... It not only has double through puts it can now send and receive at the same time. Essentially all ram before DDR5 was half duplex and now DDR5 is the first ram that is not only double data rate it also can send and receive at the same time it would take 4 dimm ddr3 sticks to make 4x64bit channels
However DDR5 does it naturally

In the ps4 there are 8 processors each with 2 channels. Thats 16 channels

if only took the 256bit tech of the DDR5 to be 4; 64bit channels than each channel would have 2 outputs and 2 inputs
so 4 times 2 times 2 = 16 channels. Of course this configuration would be paired cores in the cpu. But the benefit is that the cpu would basically always be doing calculations; over the standard ddr3 which would have lag time.

The other ideal option is that it could access the next bit of programing while it sends data to the cpu

Although I am not completely certain in how they have currently implemented the technology or how a future firmware update might make it even better. No computer on the market can do this. In most cases where there is an APU instead of a cpu+gpu combo they use DDR3 for both, not only should the APU now be able to compete with a GPu but the CPU if firmware allowed should be able to do more calculations per second with less heat and more stable power. In addition it should be able if designed right to fully integrate everything as full duplex. So in essenieces
everything will begin to act like a PCI slot connection

 

[James Mauro]

It looks like the cpu is in a paired configuration. It in actuality is TWO different 4-core Jaguar processors. So yes if firmware allows it will be the first consumer setup with a cpu configuration that is always essentially processing. There will of course be some lag time however this will be essentially reduced in comparison to todays computers. This is only achievable once you get into DDR5 sense it can send and receive and has 2 modules if they operate offset
>>>>>>>>>>>>data to module1
ram
<<<<<<<<<<<<data from module 2

and back and forth, in conjuction with the GPU which also works in the same process.

Think of it as 220 volt verse 110
Its essentially 2 different wave functions operating