Prescott delayed as i predicted

[Kelledin]

Sorry, but that doesn't even make sense. The cores themselves may be different but the packaging sure isn't. They're on completely different sockets for starters.

Do you remember the original P4 Xeon (Foster) packaging? It was basically a slightly modified Socket423 part with a socket-adapter type PCB tacked onto it bearing cache-coherency logic; this became readily apparent when some curious netizen took a nonworking Foster part and decided to take a hammer and play around with it. The more recent XeonMPs could easily much the same, so practically all Intel would have to do is take away the adapter PCB.

And there's the FSB difference which no Xeon has yet.

Only because Intel hasn't validated 800MHz FSB for server usage. Again, it's probably just a matter of choosing higher-yield parts.

Don't get me wrong, it could very easily just be a branching from the Xeon family. Personally I think that it'd have just been easier to add the L3 cache to the Pentium4 than to repackage a Xeon

That would involve a new core tapeout; compared to that, packaging is almost a trivial affair. Seeing as the cores are so similar, it's likely a Northwood with 2MB L3 cache tacked on would be the same thing as a Xeon, so the new tapeout would be kind of pointless.

And since when has Intel thought on their feet?

The unforgettable Coppermine 1.13GHz--basically a top-bin part with some extra factory OC on it. Only problem was, it didn't get tested sufficiently--I doubt Intel's repeated that mistake, but it just demonstrates how quickly they can pull a rabbit without doing a major rework.

<i>I can love my fellow man...but I'm damned if I'll love yours.</i>

 

[HardWareBoss]

Your right. That's Poopey for you. He left no banned. We'll take a poll.