Hello everyone,
I recently came across some specifications and descriptions of the RTX 4090 and the AD102 architecture. While comparing the two, I noticed a discrepancy that I would like to understand better. Specifically, I found that the RTX 4090 is said to have 11 GPCs and a 384-bit memory interface, while the AD102 architecture is described as having 12 GPCs, a 384-bit memory interface, and 12 32-bit memory controllers.
What confuses me is what happens to the one redundant memory controller in the RTX 4090, given that only one memory controller is needed for each GPC. I'm curious to know if someone can help shed some light on this matter.
From my understanding, a memory controller acts as an intermediary between the graphics card and the memory modules, managing the data transfer between them. Each GPC in the AD102 architecture is associated with a 32-bit memory controller, which makes sense considering the 384-bit memory interface. However, this leaves me wondering about the purpose of the additional memory controller.
Also, can somebody explain to me what happens after CPU sends data to GPU via PCIe? Where does the PCIe connection end up and what is done with the data before processing it in SMs?
Thank you in advance for any insights you can provide!
I recently came across some specifications and descriptions of the RTX 4090 and the AD102 architecture. While comparing the two, I noticed a discrepancy that I would like to understand better. Specifically, I found that the RTX 4090 is said to have 11 GPCs and a 384-bit memory interface, while the AD102 architecture is described as having 12 GPCs, a 384-bit memory interface, and 12 32-bit memory controllers.
What confuses me is what happens to the one redundant memory controller in the RTX 4090, given that only one memory controller is needed for each GPC. I'm curious to know if someone can help shed some light on this matter.
From my understanding, a memory controller acts as an intermediary between the graphics card and the memory modules, managing the data transfer between them. Each GPC in the AD102 architecture is associated with a 32-bit memory controller, which makes sense considering the 384-bit memory interface. However, this leaves me wondering about the purpose of the additional memory controller.
Also, can somebody explain to me what happens after CPU sends data to GPU via PCIe? Where does the PCIe connection end up and what is done with the data before processing it in SMs?
Thank you in advance for any insights you can provide!
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