According to rumor, using hydra and or sideprot, it gives the data stream the appearence of 1 core, whether its 2 or 4, then sends to driver. Rumor has it that it could be on die, or pcb, working with hydra, and using sideport for BW. Its not totally understood at this point, but thats close to what Ive seen. Look up hydra, then go by ATIs comments on the side port, then clamshell mode w/GDDR5, keeping the bus under control, with the rams speeds, and its multi device usage.
Remember, these new cards are all 40nm, so certain things need to be done for sizing, due to pad sizes etc, plus, it also makes sense in that without having to sacrifice speed going smaller on overall die size, no hot spots etc, and also, think about 4 cores, and then wanting 1Gig usage for it. Today wed need 4 gigs to meet that, and itd be a costly scenario as well