RAM - Are better CAS numbers higher or lower?

[Antidisestablishmentarianism]

For DDR3 RAM, is a higher CAS better?

 

[mrmez]

It's basically reaction time, if you like, so lower is faster/better, though real world difference is impossible to notice.

 

[unksol]

Higher is worse

 

[computertech82]

Higher is worse. And as one said, benchmarks between the cas differences doesn't make much difference.

 

[JackNaylorPE]

Lower is better.

RAM latency is CAS x 1000 / DDR speed.

So DDR3-2400, CAS 10 = 10 x 1000 / 2400 = 4.17 nanoseconds


IS DDR3-266 CAS 12 faster with respect to latency ? let's see

12 x 1000 / 2666 = 4.60 nanoseconds

Nope

How about 2133 CAS 9 ?

9 x 1000 / 2133 = 4.22 nanoseconds

 

[Tradesman1]

Normally for a slight increase going up each step of data rate you also step up one each on CL also, i.e. in jacks examples there's

2133/9 = 4.22
2400/10 = 4.17 but then jumps 2 with the CL to 2666/12 if going
2666/11 it would be even better 4.12
3000/12 = 4

 

[Pinhedd]

You're both off by a factor of two... again 😛

The effects of tCAS are negligible when used with any competently designed memory controller. The benefits of higher data rates far outweigh the benefits of lower latency.

 

[brispuss]

Lower CAS Latency is wanted, all else being equal.

Actually the base formula for calculating effective memory latency (in nanoseconds) = 2000 x CAS Latency ÷ Memory frequency in MHz

Lower Effective Latency is also preferred.

So for memory rated at CAS 12 @ 2666 MHz; effective latency = 2000 x 12 ÷ 2666 = 9.00 ns

For memory rated at CAS 11 @ 2666 MHz; effective latency = 2000 x 11 ÷ 2666 = 8.25 ns

For memory rated at CAS 9 @ 2133 MHz; effective latency = 2000 x 9 ÷ 2133 = 8.44 ns

For memory rated at CAS 10 @ 2400 MHz; effective latency = 2000 x 10 ÷ 2400 = 8.33 ns

And for memory rated at CAS 12 @ 3000 MHz; effective latency = 2000 x 12 ÷ 3000 = 8 ns <- this is the best memory with the lowest effective latency from all of the above examples.

 

[Pinhedd]

Lower CAS Latency is wanted, all else being equal.

Actually the base formula for calculating effective memory latency (in nanoseconds) = 2000 x CAS Latency ÷ Memory frequency in MHz

Lower Effective Latency is also preferred.

So for memory rated at CAS 12 @ 2666 MHz; effective latency = 2000 x 12 ÷ 2666 = 9.00 ns

For memory rated at CAS 11 @ 2666 MHz; effective latency = 2000 x 11 ÷ 2666 = 8.25 ns

For memory rated at CAS 9 @ 2133 MHz; effective latency = 2000 x 9 ÷ 2133 = 8.44 ns

For memory rated at CAS 10 @ 2400 MHz; effective latency = 2000 x 10 ÷ 2400 = 8.33 ns

And for memory rated at CAS 12 @ 3000 MHz; effective latency = 2000 x 12 ÷ 3000 = 8 ns <- this is the best memory with the lowest effective latency from all of the above examples.

You made the same mistake that they did 😛

 

[Tradesman1]

It's a combination of data rate and CL it's not one or the other, but if looking at sets that are the same data rate you want the lower CL, as I pointed out with the two 2666 examples. From there it depends on what you are doing with your rig, You can look at the theoretical numbers and explanation forever, but that's all they are as you never accomplish the theoretical i.e. theoretically dual channel is suppose to double the throughput but in reality you are doing good to get a typical increase of up to 10-15% performance increase.

 

[JackNaylorPE]

You're both off by a factor of two... again 😛

The effects of tCAS are negligible when used with any competently designed memory controller. The benefits of higher data rates far outweigh the benefits of lower latency.

1. I was speaking strictly about latency and the impact of CAS, not overall speed

IS DDR3-266 CAS 12 faster with respect to latency ?

2. I got it wrong ... well formula is correct insertions were wrong

https://en.wikipedia.org/wiki/DDR3_SDRAM

With DDR3 2400 CAS 10....

Formula of CAS x 1000 / DRAM Frequency

DRAM Frequency as reported by CPU_z on DDR3-2400 is 1200

So CAS x 1000 / DRAM Frequency = 10 x 1000 / 1200 = 8.33


3. Effects of CAS versus speed can vary by application / game and not always how we'd expect.

 

[Pinhedd]

You're both off by a factor of two... again 😛

The effects of tCAS are negligible when used with any competently designed memory controller. The benefits of higher data rates far outweigh the benefits of lower latency.

1. I was speaking strictly about latency and the impact of CAS, not overall speed

IS DDR3-266 CAS 12 faster with respect to latency ?

2. Looks like wiki got it wrong too

https://en.wikipedia.org/wiki/DDR3_SDRAM

3. Effects of CAS versus speed can vary by application / game and not always how we'd expect.

There's a reason why kids are taught never to use Wikipedia as a source starting in middleschool; it's unreliable.

The correct formula for calculating DRAM read-to-first-word-ready delay is

Delay(ns) = tCAS(cc) * tCK(ns)

tCK = 1/refclk(hz)

data rate(MT/s) = 2*refclk

DDR3-2133 has a transfer rate of 2,133 megabits per IO pin per second.

2,133 MT/s / 2 = 1,066mhz reference clock

tCK = 1/1066E6

tCK = 0.938ns

For a tCL of 9 clock cycles, the delay is 9*0.938 nanoseconds, or 8.44 nanoseconds from the clock to the first word being strobed onto the data bus.

Since DDR3 has a burst length of 8 words, corresponding to a burst period (tBURST) of 4 cycles, each subsequent word is transferred every tCK/2 cycles. The last word is strobed at (tCK/2)*7 nanoseconds after the first word and is stable until tBURST (equivalent to (tCK/2)*8) has elapsed.

First word latency = 8.44 nanoseconds

Eighth word latency = 8.44 + (0.938/2)*7
= 11.72 nanoseconds

tBURST is 4 cycles regardless of the data rate, so overclocking the memory decreases tBURST. Since tBURST lower bounds tCCD, and tCCD is what allows like column commands to be pipelined, tCL and tCWL can be nearly completely hidden by virtue of proper scheduling of memory operations; this is even easier with DDR4 than it is with DDR3.

As for that chart that you posted, it's a prime example of why Anantech's testing methodology is absolute crap. Testing "minimum FPS" is equivalent to testing "maximum global inter-frame time" without controlling for any of the countless factors that can affect that measurement. They're attempting to draw a statistical conclusion from a sample size of one.

The correct testing method is to gather a large sample size (10,000 to 100,000 frames, or a 5-10 minute run) using a synthetic benchmark and then calculate the 95th and 99th percentile frame times.