RAM Definitions ???

[chaitanya_mkin]

Hi Guys

i have some questions before i can upgrade my DDR3 RAM

1. What is SDRAM, DRAM
2. what is timing and Latency
3. whats Memory clock, I/O bus Clock and cycle time.

with all above mentioned which System RAM is best to buy for gaming and will be best performer for GTA V 😉 will be realeasing this FALL.....my mobo is ASROCK N68C-GS and CPU is FX 6300...

Please Help in detail.....

 

[aaronfield]

1. Dont worry about it. As far as im concerned you dont need to worry about it (as normal DRAM isnt manufactured i dont believe)
2. Timing and latency. Pretty much response time of the ram. Lower equals better.
3. Clock is the speed at which ram can work. I/O bus clock, dont worry about it. Cycle time is all of the "latencies" added together. pretty much how long itll take to do one "cycle".

Best ram for that board? Without price restrictions? Easy: http://www.newegg.com/Product/Product.aspx?Item=N82E16820233306&cm_re=dominator_platinum_2133-_-20-233-306-_-Product

With price and normal needs considered? Tougher but still easy:

16gb: http://www.newegg.com/Product/Product.aspx?Item=N82E16820233536

8gb: http://www.newegg.com/Product/Product.aspx?Item=N82E16820233218

Aaron

 

[Pinhedd]

Hi Guys

i have some questions before i can upgrade my DDR3 RAM

1. What is SDRAM, DRAM
2. what is timing and Latency
3. whats Memory clock, I/O bus Clock and cycle time.

with all above mentioned which System RAM is best to buy for gaming and will be best performer for GTA V 😉 will be realeasing this FALL.....my mobo is ASROCK N68C-GS and CPU is FX 6300...

Please Help in detail.....

1. DRAM is a type of memory that uses dynamic logic to store information rather than static logic.
In static logic, each memory cell is always connected to a power supply line at all times. A logic high (1) is typically represented by a high voltage level (5v, 3.3v, 2.5v, 1.8v, etc... it depends on the logic standard), and a logic low (0) is typically represented by a low voltage level (nominally 0). In dynamic logic, the memory storage element (a capacitor) is charged to the appropriate level, and then disconnected. DRAM allow for much more memory to be packed into a much smaller space while also consuming much less power, but as a consequence it's more complicated to work with. SRAM on the other hand (Static Random Access Memory) is the primary method of memory storage on the CPU itself, all cache is constructed from SRAM and the CPU registers themselves are similarly designed.
SDRAM is a variation of DRAM in which the outward facing electrical interface is clock-synchronous. All commands sent from the controller to the DRAM integrated circuit are synchronized along a clock edge, this negates the effect of signal skew as the device will ignore all commands until the clock signal arrives. Asynchronous DRAM on the other hand operates in real time, this is a real pain to work with so Asynchronous DRAM is quite rare; DRAM and SDRAM are used quite interchangeably.

2. DRAM timings are measurements in real time (nanoseconds) for asynchronous DRAM or clock cycles for synchronous DRAM. They are used by the memory controller to synchronize input and output operations. A memory device that is configured with Column Latency 7 will begin sourcing data on its IO pins 7 clock cycles after a read operation is issued to a particular memory bank. The memory controller must be prepared to select that bank and sink that data on that same cycle. If the timings aren't setup correctly the communication between the memory controller and the memory modules will not be coherent and bad things will happen. For example, the memory controller may start to sink the data one cycle too soon (and thus read garbage) or one cycle too late (and thus miss the first two words and misalign the rest). Many individuals consider tighter timings to be more desirable but benchmarks show no difference.

3. The memory clock (also called the core clock) is the internal clock frequency of the DRAM IC that controls the memory access operations. The memory clock is derived from the IO bus clock. On DDR SDRAM the memory clock is 1:1 with the IO bus clock. On DDR2 SDRAM the memory clock is 1:2 with the IO bus clock (half frequency). On DDR3 SDRAM the memory clock is 1:4 with the IO bus clock (quarter frequency).
The IO bus clock is the external clock frequency of the DRAM IC that controls the transfer of data from the memory bank to the memory controller as well as the internal memory clock. DDR memory (all variants) transfer data on both the rising edge and falling edge of the IO bus clock.

Examples:

DDR-400: Core: 200Mhz IO: 200Mhz

DDR2-800: Core: 200Mhz IO: 400Mhz

DDR3-1600: Core: 200Mhz IO: 800Mhz

As you can see, the IO interface has improved dramatically over the years while the core DRAM operation has not. The reason for this is that the DRAM integrated circuits are constructed with multiple independent memory banks which all share the same IO bus. DDR SDRAM has 4 independent memory banks, DDR2 has 4 or 8 independent memory banks, DDR3 has 8 independent memory banks, and DDR4 has 16 semi-independent memory banks organized into 4 fully independent bank groups. The memory controller can issue operations to subsequent banks while it is waiting for operations on one particular bank to complete. Thus, the increased data rate on the IO bus serves to mask the fact that the core DRAM operating speed hasn't really changed much.

 

[chaitanya_mkin]

Hi Guys

i have some questions before i can upgrade my DDR3 RAM

1. What is SDRAM, DRAM
2. what is timing and Latency
3. whats Memory clock, I/O bus Clock and cycle time.

with all above mentioned which System RAM is best to buy for gaming and will be best performer for GTA V 😉 will be realeasing this FALL.....my mobo is ASROCK N68C-GS and CPU is FX 6300...

Please Help in detail.....

1. DRAM is a type of memory that uses dynamic logic to store information rather than static logic.
In static logic, each memory cell is always connected to a power supply line at all times. A logic high (1) is typically represented by a high voltage level (5v, 3.3v, 2.5v, 1.8v, etc... it depends on the logic standard), and a logic low (0) is typically represented by a low voltage level (nominally 0). In dynamic logic, the memory storage element (a capacitor) is charged to the appropriate level, and then disconnected. DRAM allow for much more memory to be packed into a much smaller space while also consuming much less power, but as a consequence it's more complicated to work with. SRAM on the other hand (Static Random Access Memory) is the primary method of memory storage on the CPU itself, all cache is constructed from SRAM and the CPU registers themselves are similarly designed.
SDRAM is a variation of DRAM in which the outward facing electrical interface is clock-synchronous. All commands sent from the controller to the DRAM integrated circuit are synchronized along a clock edge, this negates the effect of signal skew as the device will ignore all commands until the clock signal arrives. Asynchronous DRAM on the other hand operates in real time, this is a real pain to work with so Asynchronous DRAM is quite rare; DRAM and SDRAM are used quite interchangeably.

2. DRAM timings are measurements in real time (nanoseconds) for asynchronous DRAM or clock cycles for synchronous DRAM. They are used by the memory controller to synchronize input and output operations. A memory device that is configured with Column Latency 7 will begin sourcing data on its IO pins 7 clock cycles after a read operation is issued to a particular memory bank. The memory controller must be prepared to select that bank and sink that data on that same cycle. If the timings aren't setup correctly the communication between the memory controller and the memory modules will not be coherent and bad things will happen. For example, the memory controller may start to sink the data one cycle too soon (and thus read garbage) or one cycle too late (and thus miss the first two words and misalign the rest). Many individuals consider tighter timings to be more desirable but benchmarks show no difference.

3. The memory clock (also called the core clock) is the internal clock frequency of the DRAM IC that controls the memory access operations. The memory clock is derived from the IO bus clock. On DDR SDRAM the memory clock is 1:1 with the IO bus clock. On DDR2 SDRAM the memory clock is 1:2 with the IO bus clock (half frequency). On DDR3 SDRAM the memory clock is 1:4 with the IO bus clock (quarter frequency).
The IO bus clock is the external clock frequency of the DRAM IC that controls the transfer of data from the memory bank to the memory controller as well as the internal memory clock. DDR memory (all variants) transfer data on both the rising edge and falling edge of the IO bus clock.

Examples:

DDR-400: Core: 200Mhz IO: 200Mhz

DDR2-800: Core: 200Mhz IO: 400Mhz

DDR3-1600: Core: 200Mhz IO: 800Mhz

As you can see, the IO interface has improved dramatically over the years while the core DRAM operation has not. The reason for this is that the DRAM integrated circuits are constructed with multiple independent memory banks which all share the same IO bus. DDR SDRAM has 4 independent memory banks, DDR2 has 4 or 8 independent memory banks, DDR3 has 8 independent memory banks, and DDR4 has 16 semi-independent memory banks organized into 4 fully independent bank groups. The memory controller can issue operations to subsequent banks while it is waiting for operations on one particular bank to complete. Thus, the increased data rate on the IO bus serves to mask the fact that the core DRAM operating speed hasn't really changed much.

Ohhhhh thanks alot..... need of dictionary....