RUMORS talk about a prototype called RAMPAGE of an old 3dfx vga . Protype built on the month before the disappearing of 3dfx.......
It exists and we have this one ...
read the mainly features:
Next Generation Rendering Engine (VTA)
Next Generation Video Engine
16M tri/sec, 800MP/sec, Single textured.
Programmable Shading
Higher quality filtering
T-buffer based AA
AA With 2 textures and Anisotropic with no performance hit.
AA With 4 textures with no performance hit
Scalable Architecture
Integrated Bridge functionality
Full AGP Support in SLI
Two recursion modes
Before and after W divide
Applicable for bump mapping and procedural textures
Risc-like address op instruction model
Cubic Environment Mapping
Texture Compression
DirectX/DXT ,FXT1 compressed textures
YUV Texture formats
Massive Multitexturing: 8 textures each with different
filtering: point, bilinear, trilinear, anisotropic (up to 128-tap).
Massive Iterators: 8 ARGBSTW iterators: one per texture.
Texture Recursion (Address ops) : recursion in parallel or series on up to 4 textures
Any combination of 4 recursions on the 8 available textures Recursion allows one texture to perturb the values of another texture
Texture Computer (Pixel Shader)
Massive flexible math capability
texture combine unit: (a+b)*c+d feeding...
...color combine unit: (A+B)*C+D where each abcd and ABCD can be:
from any of iterator, texture, previous, registered and constant values.
manipulated independently with: x, -x, 1-x and x-0.5.
Compare based multiplexing:
texture and color: combine unit: (a-b)? c:d and
texture combine unit output summing
R+G+B may feed
color combine unit: .(a+b)*c+d, alpha and/or color channels Useful for intensity ops, dot products.
Register based combiners
Larger color component precision
13 bits per component
Precision maintained through alpha blenders.
Alpha Blender Logic Ops
Quad pixel pipeline
4 pixels-per-clock single textured (per chip)
4/N pixels per clock for N textures (per chip)
Scalable rendering: Up to four chips ganged together. No bridge chip required.
Optimized Geometry Pipeline.
Viewport Transforms and efficient host/graphics IO yield optimum performance
Works with (or without) Sage geometry co-processor
Larger color component precision
13 bits per component
Precision maintained through alpha blenders.
Alpha Blender Logic Ops
Quad pixel pipeline
4 pixels-per-clock single textured (per chip)
4/N pixels per clock for N textures (per chip)
Scalable rendering: Up to four chips ganged together. No bridge chip required.
Optimized Geometry Pipeline.
Viewport Transforms and efficient host/graphics IO yield optimum performance
Works with (or without) Sage geometry co-processor
ecc...
and it support programmable capabilities (like newest nvidia cards)
Are you interested on talking about it ?
It exists and we have this one ...
read the mainly features:
Next Generation Rendering Engine (VTA)
Next Generation Video Engine
16M tri/sec, 800MP/sec, Single textured.
Programmable Shading
Higher quality filtering
T-buffer based AA
AA With 2 textures and Anisotropic with no performance hit.
AA With 4 textures with no performance hit
Scalable Architecture
Integrated Bridge functionality
Full AGP Support in SLI
Two recursion modes
Before and after W divide
Applicable for bump mapping and procedural textures
Risc-like address op instruction model
Cubic Environment Mapping
Texture Compression
DirectX/DXT ,FXT1 compressed textures
YUV Texture formats
Massive Multitexturing: 8 textures each with different
filtering: point, bilinear, trilinear, anisotropic (up to 128-tap).
Massive Iterators: 8 ARGBSTW iterators: one per texture.
Texture Recursion (Address ops) : recursion in parallel or series on up to 4 textures
Any combination of 4 recursions on the 8 available textures Recursion allows one texture to perturb the values of another texture
Texture Computer (Pixel Shader)
Massive flexible math capability
texture combine unit: (a+b)*c+d feeding...
...color combine unit: (A+B)*C+D where each abcd and ABCD can be:
from any of iterator, texture, previous, registered and constant values.
manipulated independently with: x, -x, 1-x and x-0.5.
Compare based multiplexing:
texture and color: combine unit: (a-b)? c:d and
texture combine unit output summing
R+G+B may feed
color combine unit: .(a+b)*c+d, alpha and/or color channels Useful for intensity ops, dot products.
Register based combiners
Larger color component precision
13 bits per component
Precision maintained through alpha blenders.
Alpha Blender Logic Ops
Quad pixel pipeline
4 pixels-per-clock single textured (per chip)
4/N pixels per clock for N textures (per chip)
Scalable rendering: Up to four chips ganged together. No bridge chip required.
Optimized Geometry Pipeline.
Viewport Transforms and efficient host/graphics IO yield optimum performance
Works with (or without) Sage geometry co-processor
Larger color component precision
13 bits per component
Precision maintained through alpha blenders.
Alpha Blender Logic Ops
Quad pixel pipeline
4 pixels-per-clock single textured (per chip)
4/N pixels per clock for N textures (per chip)
Scalable rendering: Up to four chips ganged together. No bridge chip required.
Optimized Geometry Pipeline.
Viewport Transforms and efficient host/graphics IO yield optimum performance
Works with (or without) Sage geometry co-processor
ecc...
and it support programmable capabilities (like newest nvidia cards)
Are you interested on talking about it ?
i can prove it
If you are honest because honesty is the best policy, then surely your honesty is corrupt </b></font color=orange>
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