News Report: TSMC's 5nm Process to Power Zen 4, Reportedly Already at 50 Percent Yield

InvalidError

Titan
Moderator
If density really doubles going from 7nm(+) to 5nm, AMD may need to double the entire CCD just to keep the chiplet size manageable. It would enable 8-16 cores mainstream CPUs to get made using a single CCD, which should simplify the whole design and reduce latencies all-around. By then, hex-cores should be fine getting demoted exclusively to APUs.
 

bit_user

Splendid
Ambassador
If density really doubles going from 7nm(+) to 5nm, AMD may need to double the entire CCD just to keep the chiplet size manageable.
Okay, so you're talking about cores per chiplet (CCD = Core Complex Die).

Do you foresee them increasing the CCX (i.e. Core Complex)? If so, do you think they'd go to 6 cores or 8?
 

InvalidError

Titan
Moderator
Do you foresee them increasing the CCX (i.e. Core Complex)? If so, do you think they'd go to 6 cores or 8?
The number of cores per CCX is already increasing with Zen 3 albeit with only one CCX per CCD instead of two if AMD's slides accurately depict that change and rumors say the L3 may be going up to 48MB to cash in on 7nm+'s improved density. Since the complexity of non-blocking structures usually scales with the square of endpoints, I'm going to guess first-gen 5nm won't be fast enough to support another doubling to 16-cores (3-4X the glue-logic between cores, L3 slices and fabric) without significant compromises so we'll have 8+8 instead, maybe on 5nm+ for 16 cores CCX. Would make sense for AMD to test a new process with a conservative CCX design (use two simpler CCXes per CCD to reduce the number of things that can go wrong) then merge CCXes into one after the process has matured some more.

Feeding these things is going to get interesting once we reach 32-cores CCDs. We'll likely need to go NUMA with on-package HBM3 or similar at that point to relieve the CCD-IOD bottleneck.
 
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InvalidError

Titan
Moderator
This is going to be a bunch of nonsense just like the report AMD is moving chipsets to a third party.
ASMedia has been involved in the design and manufacturing of all Ryzen chipsets except for the X570 so far and is also making the upcoming B550. The X570 designed in-house by AMD is the outlier, nothing surprising about AMD letting ASMedia handle the X670. AMD did the X570 in-house because ASMedia was not planning to have its PCIe4 ready for integration into Zen 2 chipsets in time. Hasty PCIe4 implementation is likely a signigicant part of X570's high TDP.
 
Dec 15, 2019
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Fake news. First of all you have no idea what TSMC yield is. Yield is a closely guarded secret and it is highly dependent on the design. Second, 5nm is in risk production (announced at the latest TSMC conference) and that would never happen at 50% yield. Third 5nm is now frozen for the Apple iProducts and that would never happen at 50% yield. Total click bait.
 
Fake news. First of all you have no idea what TSMC yield is. Yield is a closely guarded secret and it is highly dependent on the design. Second, 5nm is in risk production (announced at the latest TSMC conference) and that would never happen at 50% yield. Third 5nm is now frozen for the Apple iProducts and that would never happen at 50% yield. Total click bait.
Bam!

I was gonna be a smartass and say something like "oh no, Daniel Nenni says it not true so that's that". Then I did a quick Google search and if this is really Daniel Nenni then he probably knows what he's talking about.
 
Dec 15, 2019
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Also, 7nm uses the 10nm fabs so yes ramp is much faster than a greenfield fab. TSMC 5nm and 3nm will also use the same fabs so expect the 3nm yield ramp to be faster than 5nm, absolutely.
 

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