News Researchers Build Open-Source SSD Controller That Surpasses 7 GB/s

[Admin]

Primarily for academic and research purposes, this SSD is destined for the lab, not the home.

Researchers Build Open-Source SSD Controller That Surpasses 7 GB/s : Read more

 

[bit_user]

For me, the more interesting question would be what CPU core they used in it. Maybe RISC V?

From the block diagram, it looks like it could be mostly hard-wired, though. That would explain where they get the speed, and could also limit its ability to run things like FTL and do certain housekeeping tasks. In which case, it would make sense why they're not looking to commercialize it.

...hmmm, more questions than answers.

 

[Deicidium369]

For me, the more interesting question would be what CPU core they used in it. Maybe RISC V?

From the block diagram, it looks like it could be mostly hard-wired, though. That would explain where they get the speed, and could also limit its ability to run things like FTL and do certain housekeeping tasks. In which case, it would make sense why they're not looking to commercialize it.

...hmmm, more questions than answers.

No CPU core. It uses an FPGA.
https://en.wikipedia.org/wiki/Field-programmable_gate_array

They are a research lab, and have released the designs as open source.

Maybe the Most Exalted Trump created a custom RISCV implementation - he is magic, you know.

 

[CooliPi]

Seem to me to be a proof of concept, using RAM as storage. Correct me if you see actual flash.

It's useful even as it is, if the PHY and interface circuitry works, why not add any storage behind it. Garbage collection using any CPU is definitely welcome, depending on your non-volatile memory used (flash, optane, ...)

DRAM needs only self or controller helped refresh. Not a bottleneck in the whole design.

 

[bit_user]

No CPU core. It uses an FPGA.
https://en.wikipedia.org/wiki/Field-programmable_gate_array

I know what a FPGA is, thanks. Also, most larger FPGAs do have at least one CPU hard-core, but anyway...

What confused me is that the picture shows a FPGA, but then it also has a heatsink fan, under which I assumed was an ASIC. But you're right that a FPGA would make more sense for a university research lab.

Maybe the Most Exalted Trump created a custom RISCV implementation - he is magic, you know.

This is just weird. I think you've misread me.