Researchers Control Thermoelectric Voltages in CPU, Storage

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[citation][nom]greghome[/nom]So...does this mean we can get silicon smaller than 4nm ?[/citation]

You do grasp the fundamental difference between an insulation layer thickness and distances from gate-to-gate distance on a conductive silicon, right :)
 
Somehow I just don't see taking up valuable silicon real-estate on a CPU to create magnet tunnels for heat transfer control. I mean, when do you not want as much heat to leave the chip as quickly as possible? And with a common substrate, the delta-T would diminish so quickly as the chip reached steady-state, that there'd be very little thermal or current flow resulting from this phenomenon.

Now in situations in which you want to control heat flow for other reasons, such as to set a highly-stable, static heat flux on some type of sensor - I can see this perhaps being more useful. But I don't know what type of sensor might require such an environment.
 
Practical direct conversion of heat to electricity is a bit of a physics holy grail. On this small scale I wonder if this could be adapted to form a layer a chip sits on. Heat from the chip could be "recycled" and used to supplement the power needs of the chip. This tech could do wonders for battery life if the heat put off of the chips could be put to good use.
 
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