News Revolutionary Samsung tech that enables stacking HBM on CPU or GPU arrives this year — SAINT-D HBM scheduled for 2024 rollout, says report

[Admin]

Samsung paves the way for HBM4 integration with its SAINT-D interconnection and packaging technology.

Revolutionary Samsung tech that enables stacking HBM on CPU or GPU arrives this year — SAINT-D HBM scheduled for 2024 rollout, says report : Read more

 

[LabRat 891]

Yet... we still won't see a return of HBM in the consumer space.

AMD gave us a taste, and then the industry yanked it away.

 

[oofdragon]

Revolutionary..... where? Will it make processors next year make s revolutionary leap that will leave the predecessor eating dust? No? Só It's not revolutionary

 

[hannibal]

Yet... we still won't see a return of HBM in the consumer space.

AMD gave us a taste, and then the industry yanked it away.

Does not matter. This is good for datacenter products!

 

[thestryker]

I'm not sure if HBM is as sensitive to temperatures as DRAM is but this still seems like something that couldn't effectively be implemented until BSPDN nodes go live. Seems like more of an investor bait type announcement than anything industry impacting.

 

[hotaru251]

Revolutionary..... where? Will it make processors next year make s revolutionary leap that will leave the predecessor eating dust? No? Só It's not revolutionary

if the application is heavily ram influenced? very much so.

(not really useful but it is an example)
Y Cruncher for example would (i believe) benefit as its actually bandwidth bound so higher bandwidth memory (hbm) would see a significant performance increase.

i believe DDR5 caps out around 8GT/s (64GB/s) for bandwidth compared to HBM3 which can do around 100GT/s (819GB/s) and as you can imagine thats a massive performance if the application can utilize that.

Will it likely ever replace ram? no. However you could (likely) easily add a small amount and then have it spill over into dram/vram as needed.

 

[thisisaname]

if the application is heavily ram influenced? very much so.

(not really useful but it is an example)
Y Cruncher for example would (i believe) benefit as its actually bandwidth bound so higher bandwidth memory (hbm) would see a significant performance increase.

i believe DDR5 caps out around 8GT/s (64GB/s) for bandwidth compared to HBM3 which can do around 100GT/s (819GB/s) and as you can imagine thats a massive performance if the application can utilize that.

Will it likely ever replace ram? no. However you could (likely) easily add a small amount and then have it spill over into dram/vram as needed.

Sounds to me more evolutional than revolutionary.?

 

[DS426]

3D DRAM stacking on the CPU (or more specifically, on CPU logic dies) will eventually happen in the consumer world; just look at how much 3D V-Cache improved the Ryzen platform when utilized. I say g'luck on thermals, but I'm sure someone will figure it out.

 

[JRStern]

Do they really want to stack dynamic RAM for HBM? SMH

 

[Diogene7]

It would be even more revolutionnary if it would be using persistent memory / Non-Volatile-Memory (NVM) MRAM like SOT-MRAM developed by European research center IMEC : it would open plenty new oportunities !!!

https://www.imec-int.com/en/press/i...how-record-low-switching-energy-and-virtually

 

[usertests]

The promise of X-Cube finally fulfilled?

Samsung Announces Availability of its Silicon-Proven 3D IC Technology for High-Performance Applications | Samsung Semiconductor Global

Samsung 'X-Cube' enables industry-first 3D SRAM-logic working silicon at 7nm and beyond. Bandwidth and density can be scaled to suit diverse design requirements.

semiconductor.samsung.com

 

[palladin9479]

Hmm this is interesting but is going to face some pretty harsh TDP issues. High clocked DDR5 already is quite warm to the touch and on top of a 65~95W CPU die it would act as a thermal insulator. They could go with a wider 256-bit memory bus and clock the ram at half speed, would significantly reduce the thermal production but that's not good for CPU processing (great for GPU though).

 

[alan.campbell99]

The first thing that came to mind for me was “but what about thermals?”, isn’t HBM generally paired with performance processors?

 

[Albert.Thomas]

Saint D? Oh it's a dog's life...

 

[edzieba]

The article misses the most important part of this: it migrates the HBM logic die out of the HBM stack and into the host die.

Normally, a HBM 'chip' is a stack of DRAM ICs on top of a logic IC, and with the interfaces going through the logic TO to the substrate that hosts the main compute die(s). Here, the DRAM stacks go directly onto a really big logic die that hosts both the main compute and the HBM controller in one piece of monolithic silicon.