Rome in Detail: A Closer Look at AMD's 64-Core 7nm EPYC CPUs

[Guest]

AMD spills the beans on its upcoming EPYC 'Rome' processor, with up to 64 Zen 2 cores.

Rome in Detail: A Closer Look at AMD's 64-Core 7nm EPYC CPUs : Read more

 

[sstanic]

so where's the detail?

 

[shpankey]

amd on a role

 

[milkod2001]

Just wondering if with PCIe 4.0 will be also get faster m2. SSD drives or it will be the same. Also what other real benefits are coming from PCIe 4.0?

 

[RememberThe5th]

pcie should give more bandwith, but current gpus and m.2 still havent reached limit of pcie 3.0 or 2.0 limit yet, in short not even close.

 

[bit_user]

Thanks to this improved design, each chiplet can access the memory with equal latency.

I don't want equal latency to come at the expense of low latency. The current EPYC architecture provides low latency for local memory accesses, which can be achieved though NUMA-aware apps, OS, and/or VM partitioning.

I hope AMD didn't just cede ground on one of EPYC's strengths.

 

[bit_user]

Just wondering if with PCIe 4.0 will be also get faster m2. SSD drives or it will be the same. Also what other real benefits are coming from PCIe 4.0?

The main benefit for consumers (and we still don't know when it will arrive in a consumer platform) will be that you can do more with fewer PCIe lanes. So, splitting your GPU lanes to dual x8 will be virtually painless, as will splitting your M.2 to dual x2 connections.

Personally, I'm most interested in seeing full-rate 10 Gbps ethernet on a little PCIe 4.0 x1 card.

pcie should give more bandwith, but current gpus and m.2 still havent reached limit of pcie 3.0 or 2.0 limit yet, in short not even close.

Yes, they have exceeded what PCIe 2.0 can support, as that's < 2 GB/sec for a x4 link (or a x2 link @ PCIe 3.0).

 

[RememberThe5th]

Well I've meant for the x16 lanes, I havent seen or watched around the m.2 and x2/x4/x8 modes and transfer rate, but its good to know.

 

[redgarl]

PCIe 4.0 seems to be important for AMD because of this:

https://images.anandtech.com/doci/13547/1541527920197687529224_575px.jpg

01:03PM EST - Infinity Fabric GPU to GPU at 100 GB/s per link

01:03PM EST - Infinity Fabric GPU to GPU at 100 GB/s per link

01:03PM EST - Without bridges or switches

01:03PM EST - Connected in a ring

01:03PM EST - Helps scaling multiGPU

 

[RememberThe5th]

Atleast they didnt stick to the same "PCIE LANES" as Intel over the course of the years...

 

[stdragon]

I can imagine the TDP being at least 200 watts under full load. But how much more than that?? I mean, I get 7nm is more efficient than 14nm at the transistor level, but there's also a lot more dies on that package too. Will be very interesting on cooling strategies for a racked up server that uses as few U's as possible.

 

[gasaraki]

OK, so from this article, you say that the Rome processor will have Zen 2 "chiplets" and PCIe 4.0 lanes. So you are saying that Zen 2 will contain PCIe 4.0 lanes unless the PCIe 4.0 lanes have been moved out on to the I/O processor. If that's the case then the chiplets have to talk to the IO processor via Infinity Fabric 2.0 then to the PCI bus. Seems like that would increase latency.

 

[hannibal]

That us the general consessus. There is more latency but separate IO can feed separate cpus more evenly. So you win something and lose something. Intersting to see bencmarks! They did not change the system for no reason!

 

[Peter Martin]

I bet Rome wasn't built in a day..... rofl

 

[Swisscheesy]

7nm? Wow.

 

[stdragon]

I bet Rome wasn't built in a day..... rofl

Well, given it burned for 6 days after...

 

[adrianxw]

I'm wondering about the cooling of these beasts. That is a lot of cores and threads, if you run BOINC or another platform like that, all cores and threads are in use pretty much all the time. Clock speed is not mentioned.