Discussion Ryzen 5 5600X UV (per core CO) magic and Prime95 4 threads testing and per thread fail (FIXED on my own)

DimkaTsv

Great
Nov 7, 2021
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95
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I have such a question.
Currently working on UV of my R5 5600X and met one solid problem
Currently i am going TDP/TDC/EDC of 78/72/108 (just 120% of base limitations), with +50 mHz boost overdrive and curve of -28 -30 -30 -27 -28 -28 with core order 6 1 2 4 3 5 (means 1+2 are first 2, 4+3 are second pair and 0+5 are third pair basically)
When i run Prime95 (small FFT with AVX2 on) on 6 cores it's fine (and load is 100%)
But when i run it on 4 or 2 core, i meet huge problem... Threads begin to fail 1 by 1, beginning from last in order. except main one or first two... They drop not at once, but one by one with some time interval (around 30 secs to minute, maybe even more for last one)
And more of than, effective core of that last thread always not equal to others. That means i have 3 cores of 4.4-4.55 gHz and last one is 2.5-3.5 gHz
Same situation with cores effective clock happens even when i turn AVX off completely in test, but with AVX off threads don't fail suddenly at all.

Is it really undervolt problem? or just AVX instruction on 5600X shennanigans? Because with CO set to 0 on core 3 it results same, as with -27...

My main concern is... well it was stable some time ago, at least more stable...
And it can work stable sometimes too, even without turning off AVX2. But sometimes threads just begin to fail one by one in very specific order from last core to first. And it doesn't happeт without AVX instructions or happen MUCH more lately it seems. . . will look into that

Like just now i run first selftest successfull, but it only took me to open up prime95 window, when on my eyes one thread died. And second thread 40 seconds later

UPD: yeah, it seems it is UV problem, at least with CO disabled completely it doesn't fail, at least on first glance
Now i want to know, why CO -0 on C3 didn't stopped it from failing, while disabling CO overall stopped it

UPD2: Set up CO on core 3 to -15, and it magically started working, -16 already fails at some point... Now new question. Was it core 3 that caused chained thread fail and i can set up UV of core 4 to -25 and lower? Or core 4 can fail on itself (hadn't seen that even once yet though... only after core 3)?

UPD3: It seems that core voltages are entangled somehow...
Stable line rn 28-30-28-15-20-28
Change core 3 to -16 - it fails
Change core 4! to -22 - instant core 3+4 fail
Change core 2! to -30 - instant core 3+4 fail!!!
HOW DOES THIS WORK?!
It is as if power line actually chains through C1-2-4-3-0-6 in that specific order, and not divided... So it takes in account CO values for cores that went before one you are testing...

UPD4: Yup, after fixing base clock from 99.8 to 99.98 (100 in BIOS) and increasing PBO TDP limit to 85 i got another 3+4 core thread fail in Prime95... and fixed it by changing, guess what? Yeah, i set up my PBO CO on core 2!!! from 28 to 27, and it is now stable again...

Conclusion. Guys, if your threads becoming unstable after PBO CO per core settings, it may not be that this specific core settings are wrong... It may be that PREVIOUS core setting is too severe...
So if you have core priority 0-1-2-3-4-5-6 and your core 3 fails, maybe it is not that your core 3 UV was too big... it maybe that your cores 1 or 2 UV was too big instead! Losing stability on one core, can affect all cores in performance order after unstable one

If anyone can explain, why it works like that i would be grateful
 
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