News Ryzen 5 9600X benchmarks show doubled cache bandwidth improvements — leaked AIDA64 benchmarks point to much faster L1 and L2 cache

[Admin]

A Ryzen 5 9600X engineering sample was tested in Aida64's memory benchmark, proving that AMD's Zen 5 L1 and L2 cache improvements are real.

Ryzen 5 9600X benchmarks show doubled cache bandwidth improvements — leaked AIDA64 benchmarks point to much faster L1 and L2 cache : Read more

 

[Deleted member 2731765]

And......this is just an early engineering sample being tested here, so the final performance should end up even better, both in synthetic and real world gaming tests.


Some rumors I would like to point out here. Kind of off topic though.

First off, as per Club386, AMD is already prepping for its next-gen 3D V-Cache variants of the Granite Ridge Ryzen 9000 series processors. But to me, this seems highly 'unlikely', because there would only be a 2 months release window time gap, between non-X3D variants, and next-gen 3D V-Cache chips.

Makes little practical sense, since there won't be any serious competition from Intel until late 2024, since Arrow Lake-S chips aren't coming out in next few months or so.

IDK, but this is what they had to say:

"Our source on the Computex show floor tells us AMD plans to launch 9000X3D processors in September. This matches the staggered release of X870E motherboards that we anticipate will arrive the same month.

There’s no hard indication of which CPUs will arrive first, but an educated guess from historical releases suggests it’ll likely start with Ryzen 9 9950X3D and possibly Ryzen 9 9900X3D.

There was a level of confidence behind our source’s words, and they’re trustworthy enough to put stock into. That said, familiarity with how nebulous AMD’s launch schedules are urges taking this with a pinch of salt. Nothing’s confirmed until you have a sample in your hand as dates can easily change." ----- via Club386

Next up, AMD's senior technical marketing manager, Donny Woligroski, revealed that the firm is indeed working on future "X3D" processors. It appears AMD is working on some cool new features for its next-gen Ryzen 9000X3D "3D V-Cache" family.

He mentions "cool differentiators" here. Not sure what AMD means by this, but an educated guess would imply that the firm might be working on varied and different 3D V-Cache configurations for its Ryzen 9000X3D CPU lineup.

Varied sizes of 3D V-Cache to further segment the 9000 series lineup, or something else entirely ?

The X3D stuff, we have a lot to say about it. The best part about it is we're not just resting on laurels. We're improving what we can do with X3D, it's really exciting and I'm super looking forward to talking to people about that.

It's not like, hey, we've also added X3D to a chip. We are working actively on really cool differentiators to make it even better. We're working on X3D, we're improving it.

Donny Woligroski - AMD Senior Technical Marketing Manager (via PC Gamer)

EDIT:

BTW, we have already seen LAB samples featuring dual 3D V-Cache stack Ryzen chips from AMD before, in their labs, but I doubt AMD would go this route even for the Ryzen 9000 series lineup, due to higher cost, power, and thermal drawbacks.

 

[Evildead_666]

And......this is just an early engineering sample being tested here, so the final performance should end up even better, both in synthetic and real world gaming tests.


Some rumors I would like to point out here. Kind of off topic though.

First off, as per Club386, AMD is already prepping for its next-gen 3D V-Cache variants of the Granite Ridge Ryzen 9000 series processors. But to me, this seems highly 'unlikely', because there would only be a 2 months release window time gap, between non-X3D variants, and next-gen 3D V-Cache chips.

Makes little practical sense, since there won't be any serious competition from Intel until late 2024, since Arrow Lake-S chips aren't coming out in next few months or so.

IDK, but this is what they had to say:




Next up, AMD's senior technical marketing manager, Donny Woligroski, revealed that the firm is indeed working on future "X3D" processors. It appears AMD is working on some cool new features for its next-gen Ryzen 9000X3D "3D V-Cache" family.

He mentions "cool differentiators" here. Not sure what AMD means by this, but an educated guess would imply that the firm might be working on varied and different 3D V-Cache configurations for its Ryzen 9000X3D CPU lineup.

Varied sizes of 3D V-Cache to further segment the 9000 series lineup, or something else entirely ?

Could they layer an AI die with the X3D die ?
Or another compute type die ?

That would certainly be a differentiator.

Companies have talked about having "extra's" within memory die's, so there's thaat ...

 

[TerryLaze]

He mentions "cool differentiators" here. Not sure what AMD means by this, but an educated guess would imply that the firm might be working on varied and different 3D V-Cache configurations for its Ryzen 9000X3D CPU lineup.

Varied sizes of 3D V-Cache to further segment the 9000 series lineup, or something else entirely ?

Senior Technical Marketing Manager

Is super looking forward to actively work on something really cool...

View: https://www.youtube.com/watch?v=GyV_UG60dD4

 

[jeremyj_83]

BTW, we have already seen LAB samples featuring dual 3D V-Cache stack Ryzen chips from AMD before, in their labs, but I doubt AMD would go this route even for the Ryzen 9000 series lineup, due to higher cost, power, and thermal drawbacks.

Could they be doing something like putting the 3D V-Cache on the IOD instead of the cores. While that would have longer latency than standard 3D V-Cache, it would make the latency the same for due CCD chips, allow for clocks to stay the same, and be lower latency than going to RAM. Heck might even be able to act like Infinity Cache and give more effective RAM bandwidth.

 

[TechyIT223]

Superb! Keep them rumors incoming

 

[artk2219]

Could they be doing something like putting the 3D V-Cache on the IOD instead of the cores. While that would have longer latency than standard 3D V-Cache, it would make the latency the same for due CCD chips, allow for clocks to stay the same, and be lower latency than going to RAM. Heck might even be able to act like Infinity Cache and give more effective RAM bandwidth.

I could see that being something thats done on the server side, but not something that they would do on the client side just yet. Those 3D Vcache die's are not the cheapest things to manufacture, its why its only on some CPU's and why they cost extra. Making that part of the IO die that every cpu uses would be more expensive than its worth for the consumer side. On the professional side they could probably make it work if they can get the margins to work out. That said, 3D Vcache is still fickle, not everything benefits from the extra cache, and for many uses its just something extra that isn't being used. Sure you could offer models with it fused off or fuse it off on die's that have a defective cache portion. But you could also just make it a separate die and only sell it on certain SKU's for people that know they need it, and for whom it would be a benefit. Maybe in the future if it becomes cheap enough they may throw it on every CPU, but probably not for a while.

 

[jxdking]

Could they be doing something like putting the 3D V-Cache on the IOD instead of the cores. While that would have longer latency than standard 3D V-Cache, it would make the latency the same for due CCD chips, allow for clocks to stay the same, and be lower latency than going to RAM. Heck might even be able to act like Infinity Cache and give more effective RAM bandwidth.

The bandwidth of the infinity fabric between IOD and CCD is not great. If 3D V cache is on the IOD, it won't benefit much comparing access DDR5 directly.

I believe there are couple improvements that they can do based on the 7000x3D. They can put v cache under the CCD, instead of on top of the CCD. That will solve the most thermal issue. Also, they can combine v-cache with Zen5C CCD. As Zen5C won't clock high anyway, there will be minimum clock drop.

 

[abufrejoval]

The biggest issue with V-cache (VC) at the moment is that while the production makes it a hard coded choice, your use cases might benefit from more clocks (~VC) or bigger caches (VC), both can't be had, evidently...

What we don't know is how much of the clock gap between VC and ~VC chips is a) added operational power for the VC b) impeded heat dissipation from the extra layer c) voltage restrictions imposed via VC.

So if it's mostly a) and c) but not so much b), you could turn a VC chip in pretty near a ~VC chip simply by deactivating the extra cache, flushing it first and then setting some magic registers to have it go passive.

It might take a moment, it might only work at the granularity of a CCD, but especially in EPYCs it would make some HPC customer really happy to have that choice.

And since that makes it scot-free also for desktops, it's another ace someone might just want to play a little earlier this time around, especially since it really would push those EPYC sales.

 

[Lucky_SLS]

The 7000X3D parts were hamstrung by voltage and thermal limitations, If AMD finds a workaround to let the 9000X3D chips to boost to its full potential, its a great win for them!

 

[abufrejoval]

Twice the bandwidth is definitely an interesting tidbit. Now I'd only want the sizes of the L1/2 quoted inside the article or the table (not everyone has them in their head), and an honorable mention or comparison to Intel would also have the reader run around a little less.

Doubling the bandwidth clearly means doubling the wires and that is a rather horrible expense in a multi-masking process, but reduces it much more to a surface area sacrifice in EUV.

So it's one of the things where we can see how process transitions also shift chip design decisions in rather distinct manners (if I'm not totally mistaken).

 

[Notton]

That table is hard to read.
The comparison should be against L1 vs L1 and L2 vs L2, but the way it's listed makes it look like L1 vs L2.

 

[Deleted member 2731765]

That table is hard to read.
The comparison should be against L1 vs L1 and L2 vs L2, but the way it's listed makes it look like L1 vs L2.

Yup a bit confusing. Maybe this breakdown is more clear ?

L1 Cache Bandwidth in GB/s (Read / Write / Copy / Latency):

• Ryzen 5 9600X (ES): 3756.4 / 1884.4 / 3755.9 / 0.8ns
• Ryzen 5 7600X: 2029.6 / 1026.9 / 2048.1 / 0.7ns

L2 Cache Bandwidth in GB/s (Read / Write / Copy / Latency):

• Ryzen 5 9600X (ES): 1874.6 / 1795.1 / 1859.7 / 2.8ns
• Ryzen 5 7600X: 1028.5 / 1017.0 / 1017.6 / 2.6ns

L3 Cache Bandwidth in GB/s (Read / Write / Copy / Latency):

• Ryzen 5 9600X (ES): 782.08 / 771.46 / 772.32 / 10.1ns
• Ryzen 5 7600X: 847.82 / 854.86 / 822.01 / 9.7ns

Here cometh another leak ! Now, the same sample chip was also tested in CPU-z with an overclock of 5.7 GHz, or a +300 MHz boost over its stock boost clock of 5.4 GHz.

Btw, this OC/overclock was done across all cores, while the chip's 5.4 GHz frequency is a single-core boost with the average all-core boost rounding up around 5.0-5.1 GHz.

But we all know, CPU-Z score is a bad metric for comparison, at least for AMD Ryzen CPUs. CPU-Z app never took advantage of Zen4's improvements to the arch like, micro-op cache, branch prediction, L2 cache capacity etc, but other apps did.

I expect the same with ZEN 5.

So it's not worth the time comparing these 1T and NT scores. We also don't know anything about the test environment being used here. But this 65 Watt chip has OC potential it seems. TSMC 4nm also seems to play a role here !

 

[ingtar33]

I think the plan is to launch the x3D chips just before or at the same time intel launches their next gen chips.

 

[Deleted member 2731765]

But to me, this seems highly 'unlikely', because there would only be a 2 months release window time gap, between non-X3D variants, and next-gen 3D V-Cache chips.

To further quote myself, the Ryzen 5000 series 3D V-Cache X3D parts came out roughly 17 months later, the 5800X3D SKU, after the release of 5800X.

And the 7800X3D SKU came out roughly 7 months after the vanilla variant 7700X got released in September 2022. So a 2 months release Window for Ryzen 9000 X3D series seems odd to me.

A bit too quick for AMD to capture sales of the vanilla counterparts, IMO !

Could they layer an AI die with the X3D die ?
Or another compute type die ?

Are you talking about adding an NPU here ? Because these chips don't have any AI die. But not feasible to do that in my opinion. They can use DUAL 3D V-cache chiplets though, but again, this idea is not economical.

 

[TheJoker2020]

Doubling the bandwidth clearly means doubling the wires

Not necessarily, doubling frequency would also do it and there are a myriad of other ways of making improvements and typically it will be a mixture of several things.

I look forward to this being explained in depth by a good tech journalist when all of the nitty-gritty is released (typically right after the hard launch)

 

[Deleted member 2731765]

I think the plan is to launch the x3D chips just before or at the same time intel launches their next gen chips.

That's what the actual launch plan should be if AMD really wants to be in a much better competitive position in the CPU market. Launching early within a 2 months period gap might also cannibalize the sales of the vanilla non-X3D chips as well, imo.

 

[thestryker]

That's what the actual launch plan should be if AMD really wants to be in a much better competitive position in the CPU market. Launching early within a 2 months period gap might also cannibalize the sales of the vanilla non-X3D chips as well, imo.

Given that motherboards based on the "new" chipsets weren't supposed to launch anytime soon to the point that some vendors were surprised that AMD was going into detail now and letting them be shown makes me wonder if AMD has been shifting the Zen 5 launch around. It just seems like an odd time to be releasing new CPUs while announcing new motherboards that aren't going to be available.

I also find it hard to believe they have anything to really worry about with ARL, not that it won't be good, but it would have to be extremely good to rain on AMD's parade. Perhaps I'm wrong about this and they're going to move the X3D chips up to a Q4 2024 release to keep their leadership position.

 

[TechyIT223]

Even the x870 motherboard models are not launching on time let alone these X3D chips.

 

[TerryLaze]

Launching early within a 2 months period gap might also cannibalize the sales of the vanilla non-X3D chips as well, imo.

Would it though?! Anybody that considers an x3d chip is just going to wait for them to release to look at reviews and decide what to get, anytime something new is on the horizon sales of current stuff goes way down.
AMD probably just can't afford for people to 'wait and see' and needs sales as fast as possible.

 

[abufrejoval]

Even the x870 motherboard models are not launching on time let alone these X3D chips.

The x870 mainboards are simply not required nor are they bound to be very different from the x600 boards that should just work with these new SoCs, after a BIOS update.

The switch chips are the same vendor and arrangements the main difference USB4 validation and perhaps having actually been tested with Zen 5 SoCs.

There is no technical reason to imply a chained dependency here.

 

[TerryLaze]

The x870 mainboards are simply not required nor are they bound to be very different from the x600 boards that should just work with these new SoCs, after a BIOS update.

We can't know that, this article is about faster cache, do you know for a fact that the old boards can support the cache speed with an bios update?!
We also saw the overclock and that's another thing we don't know about, maybe you will need better VRMs than the current boards have.

Maybe the old boards will be fine and will be able to do all of this, but it's just a guess.

 

[TechyIT223]

The x870 mainboards are simply not required nor are they bound to be very different from the x600 boards that should just work with these new SoCs, after a BIOS update.

The switch chips are the same vendor and arrangements the main difference USB4 validation and perhaps having actually been tested with Zen 5 SoCs.

There is no technical reason to imply a chained dependency here.

How do you know they'll not be required?

X870 boards will have some extra tech features for sure we are not aware of yet. Rumors have already hinted about this

 

[Deleted member 2731765]

Would it though?! Anybody that considers an x3d chip is just going to wait for them to release to look at reviews and decide what to get, anytime something new is on the horizon sales of current stuff goes way down.

Yes, it does matter. Also, not everyone wants the "fastest" X3D gaming chip. Most gamers would be interested more in the vanilla parts. And there is this price gap difference as well.

But if we go by this recent article/news, the AMD CPU landscape looks a bit different at for this generation of AMD CPUs. So consumer's buying habit/trend might also change this time.

So can't say anything with surety what's gonna happen, and also whether AMD's 2-month release date decision for the X3D parts is indeed true or not.

https://www.tomshardware.com/pc-com...heyll-be-close-improved-3d-v-cache-coming-too

 

[abufrejoval]

How do you know they'll not be required?

Mostly, because AMD has said so themselves.

And if they were, they'd get rather bad press about violating their backward compatibility promise.

And then it wouldn't be that easy, because the ASmedia chips on the board, which provide most of the extra functionality, that doesn't come off the IOD itself, is/are the very same ASmedia chip(s) they use on the 600 series: can't teach an old pony fundamentally new tricks.

One might argue that they left USB4 functionality somewhat unfairly on the table in the last round and that it should be possible even on existing hardware. My x670 board has a BIOS option to enable USB4, but I haven't gotten around testing it, nor is the board documentation even clear which of the ports that might affect.

Or if it even makes a difference because USB4 is very long list of options, few of which are required to carry that label.

X870 boards will have some extra tech features for sure we are not aware of yet. Rumors have already hinted about this

I'm sure they'll try to think of something appetizing.

It's not an easy balance to strike between those customers, who simply expect everything new and shiny and those who want to enjoy and profit from AMD changing as little as possible for the biggest improvement possible.

My main argument is that there isn't a mandatory or hard dependence chain and AMD can move its invidual pieces on the PC market chessboard how they see fit: Intel doesn't have that flexibility and I can imagine one or three engineers at AMD gleefully poking that at them.

Perhaps another point would be that V-cache is a technology that was invented for EPYC, consumer hardware is mostly a welcome windfall. So its availability and features won't soley be driven by consumer demands or opportunities.