News Ryzen 7000 3D V-Cache CPUs May Offer Even More Bandwidth Than First-Gen Counterparts

[Admin]

Tom Wassick has seemingly discovered more TSVs on Ryzen 7000 parts compared to Ryzen 5000, suggesting a bandwidth upgrade compared to first-gen 3D V-Cache chips.

Ryzen 7000 3D V-Cache CPUs May Offer Even More Bandwidth Than First-Gen Counterparts : Read more

 

[TR909]

Would be nice to see higher clocks (close to non3D ones) and better non-gaming performance compared to zen3.

 

[Mattzun]

Non-gaming performance seems to be mostly related to core count.
The5800x3d is about the same speed (or slower) than a 5800x in Cinebench and I don't see that changing (heat dissipation will still be an issue)

If the ECO 105 mode on the 7700x provides 95 percent of the performance of unlocked power limit on the same chip, the 7800x3d should be amazing for CPU limited gaming on really high end GPUs.
This seems to be a rather small niche (MSFS fans who don't like frame generation, Spiderman with ray tracing on, some 1080p games)
A 13600k or a 5800x3d seems good enough for even a 4090 in most games.

 

[-Fran-]

Let's see how it does on benchmark day.

I'm certainly optimistic, but if my 5800X3D is any indication, they do have a few things to improve (vs the non-VCache) in order to make those unstoppable. One is the chips running a tad hotter than a comparable 5800X, so I'll imagine Zen4 is not going to change that too much. Given how these now just happily go to 95°C, maybe they've already started hiding the temps? Maybe?

A hot take, perhaps, but for me at least the "real" temperature of the CPU is important. I hope they improve the IHS for it, somehow.

Regards.

 

[escksu]

I have to say the biggest challenge is to get software companies to support it. The real deal isn't in gaming desktop CPUs, it's in the high end servers.

Right now, only very few apps benefit from the epyc CPUs with additional cache. So, alot more needs to be done.

 

[TerryLaze]

I have to say the biggest challenge is to get software companies to support it. The real deal isn't in gaming desktop CPUs, it's in the high end servers.

Right now, only very few apps benefit from the epyc CPUs with additional cache. So, alot more needs to be done.

You can't magically support something just because you want to.
If your code uses a lot of data that stays the same (7zip inbuild bench that uses a fixed dataset of 32Mb) it will automatically benefit from the cache, we have seen that from the first gen of zen cpus, if it uses less data or the data changes often then cache will give less or no benefit.
If devs could do that they would do it since day one because it would be great advertising for them showing their code run that much faster, it's not like devs don't want to make more sales.

 

[KraakBal]

Disagree. The whole point of cache is to be transparent to software, and should always benefit where memory access is a lot.

Software can though and is very rarely optimized for specific cache sizes. But only generally to make it fit in a particular smaller target cache size.

You have to understand that some loads just don't access memory that often by their nature, so will not see the increase of more cache. Games actually seems to benefit most of the time

 

[George³]

Forgive a question from someone with insufficient knowledge, but ... How does increasing the contact area between the cache layer and the CPU logic below magically help to achieve higher throughput? It's not like running water through two pipes of different diameters, is it?

 

[jkflipflop98]

Forgive a question from someone with insufficient knowledge, but ... How does increasing the contact area between the cache layer and the CPU logic below magically help to achieve higher throughput? It's not like running water through two pipes of different diameters, is it?

In this instance they mean that AMD is putting in more pipes so more water can flow in faster. Not that the pipes themselves are getting bigger (they're actually getting smaller)

 

[George³]

I waiting for logical answer not for analogical.
Is more "pipes" fit to wider bus. Like different between 128bit bus and 256bit bus?

 

[cc2onouui]

Let's see how it does on benchmark day.

I'm certainly optimistic, but if my 5800X3D is any indication, they do have a few things to improve (vs the non-VCache) in order to make those unstoppable. One is the chips running a tad hotter than a comparable 5800X, so I'll imagine Zen4 is not going to change that too much. Given how these now just happily go to 95°C, maybe they've already started hiding the temps? Maybe?

A hot take, perhaps, but for me at least the "real" temperature of the CPU is important. I hope they improve the IHS for it, somehow.

Regards.

X3D will be a lot better than regular 7000s from thermal perspective because of the extra layer it will allow for thinner IHS.. this definitely will dominate (my guess) also in multi threaded workloads because ZEN 7000 can boost "all cores" over 5,5 GHz with better thermal (not sure they will boost the clocks though as the voltage could be a limit again), the small mistake AMD did with the IHS made all the doubts about a high performer they shouldn't respect the AM4 cooler compatibility

 

[The Historical Fidelity]

X3D will be a lot better than regular 7000s from thermal perspective because of the extra layer it will allow for thinner IHS.. this definitely will dominate (my guess) also in multi threaded workloads because ZEN 7000 can boost "all cores" over 5,5 GHz with better thermal (not sure they will boost the clocks though as the voltage could be a limit again), the small mistake AMD did with the IHS made all the doubts about a high performer they shouldn't respect the AM4 cooler compatibility

Absolutely not, silicon is a terrible thermal conductor, so stacking silicon above the hot cores is much more detrimental to performance vs the benefit of thinning out the copper IHS which is an excellent thermal conductor.

 

[Wisecracker]

Magic 8-Ball says: "Remains to be determined"

The 7nm AMD Ryzen 7 5800X3D has 64MB 3D V-'4th-level Cache' ___ The 3D V-Cache is ever so slightly slower than the L3 baked into the CPU with an increase in latency of 3 nanoseconds.

MUCH better than the 50ns-90ns that would be incurred if the CPU had to wait for data to be fetched from system RAM.

Let's say the 6nm AMD Ryzen 7 7800X3D and Ryzen 9 7950X3D has 96MB 3D V-'4th-level Cache' ___ in the same die area as the 7nm that results in an increase of 30% in last-level cache 'hitting'

The current TSVs enable bandwidth between them of up to 2TB per second BUT the Internets claim "increase of 30% in last-level cache 'hitting' ..."

YOU make the call !
( by early 2023 ___ at CES? )

Forgive a question from someone with insufficient knowledge, but ... How does increasing the contact area between the cache layer and the CPU logic below magically help to achieve higher throughput? It's not like running water through two pipes of different diameters, is it?

I waiting for logical answer not for analogical.
Is more "pipes" fit to wider bus. Like different between 128bit bus and 256bit bus?