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[TerryLaze]

LOL. You're kidding, right? I just spent like half a day defending the idea of hybrid CPUs for desktop, over in this thread. The only thing I took issue with here, was the false equivalence @KyaraM drew between Alder/Raptor Lake's E-cores and Zen 3/4 cores.

That you have to seize on such a simple and self-evident observation to score some kind of points speaks for itself. I guess if you see the world through partisan eyes, it's hard to see anything but partisan motives in anyone else.

So what exactly is your issue then with what kyara said?
The 13900k will have 24cores while the 7950x will have 16.
So 16 of the 13900k cores will be e-cores but still cores, how close are they going to be to the performance of zen4 cores at whatever clocks the zen4 cores might manage when all cores are loaded? Nobody knows, but it's also not the point.
They won't be as strong as the p-cores or as the zen 4 cores, but as you also recognized neither are the p-cores or the zen4 cores when you load many of them with work.

So what was even the point of you pointing out that e-cores aren't zen 4 cores?
They are still counting towards the multuithreaded performance and they still use up power.

 

[bit_user]

So what was even the point of you pointing out that e-cores aren't zen 4 cores?

Because it was a disingenuous argument, and if we're serious about having any kind of productive discussions around here, then such points shouldn't go unnoticed.

They are still counting towards the multuithreaded performance and they still use up power.

No one said otherwise. The way @KyaraM was directly comparing core counts implicitly treats them as the same class of cores, which we all know they're not.

 

[KyaraM]

LOL. You're kidding, right? I just spent like half a day defending the idea of hybrid CPUs for desktop, over in this thread. The only thing I took issue with here, was the false equivalence @KyaraM drew between Alder/Raptor Lake's E-cores and Zen 3/4 cores.

That you have to seize on such a simple and self-evident observation to score some kind of points speaks for itself. I guess if you see the world through partisan eyes, it's hard to see anything but partisan motives in anyone else.

More cores usually mean more power draw and lower clock speeds. E-cores allow the CPU to run at higher speed with a higher core count than otherwise possible. There is no disingenuity in my comment. You get more cores for a similar envelope, that all can run at their maximum speed, which shows in benchmarks. Core power doesn't matter so much past a certain point even for multi-threaded applications, as stated several times here before. However, each individual core increases power draw; their strenght doesn't really change that, at most it changes how high the additional draw is. So, yes, it does matter if you have 16 cores that clock at 2/3rds the max speed, or 24 where 8 clock at almost their max speed and the other 16 at 2/3rd the speed of the others. Those aren't exact numbers, only very rough estimates, so please refrain from picking them apart. And, yes, the allowed power matters, too, of course it does. But multi-core, I would still expect the CPU with more cores to put out more performance than the one with less but stronger cores. Isn't that the entire premise of server CPUs after all?

 

[bit_user]

More cores usually mean more power draw and lower clock speeds. E-cores allow the CPU to run at higher speed with a higher core count than otherwise possible. There is no disingenuity in my comment. You get more cores for a similar envelope, that all can run at their maximum speed, which shows in benchmarks. Core power doesn't matter so much past a certain point even for multi-threaded applications, as stated several times here before. However, each individual core increases power draw; their strenght doesn't really change that, at most it changes how high the additional draw is. So, yes, it does matter if you have 16 cores that clock at 2/3rds the max speed, or 24 where 8 clock at almost their max speed and the other 16 at 2/3rd the speed of the others. Those aren't exact numbers, only very rough estimates, so please refrain from picking them apart. And, yes, the allowed power matters, too, of course it does. But multi-core, I would still expect the CPU with more cores to put out more performance than the one with less but stronger cores. Isn't that the entire premise of server CPUs after all?

The issue is a very simple one, and it doesn't take so many words to understand. The E-cores are neither as fast, nor do they use as much power as P-cores. Therefore, they should not be seen as equivalent to P-cores, and you obviously don't. However, when you say:

"The 13900k has a limit of 250W. The 7950X has a limit of 230W for far less cores."​

...it sounds as if you're suggesting otherwise (i.e. by directly comparing core counts). That's a false-equivalence. If you don't mean to imply they're equivalent, then don't. It's really that simple.

Now, I'm going to point something out, in case you don't know. From your above explanation, it sounds as if you're saying the performance difference is simply due to clock speed. However, even Intel doesn't make this claim. They have said the Alder Lake E-cores perform similar per-clock as Skylake cores. Benchmarks have also shown Alder Lake's P-cores to run 67% to 85% faster (single-threaded), yet their peak clocks are not 67% to 85% higher than the E-cores'. That's further evidence that the performance differences between the cores are a lot deeper than simply clock speed.

 

[-Fran-]

Funny how in the Bulldozer times peple was like "but IPC is king! number of cores is moot" when AMD claimed 8 "proper" cores (which it wasn't, in all honesty). Intel's bigLITTLE is just what AMD did with Bulldozer, but better: BD sacrificed Float over INT throughput and AlderLake sacrificed AVX512 over moar cores and a bit of efficiency for the whole SoC (increasing through put, like BD wanted to do as well). That's perfectly valid as long as the trade offs are understood.

Interesting how Zen4 will take a similar approach for AVX512 as BD did back in the day. Zen5 should have full fat AVX512 support, from what I understand.

Regards.

 

[bit_user]

Funny how in the Bulldozer times peple was like "but IPC is king! number of cores is moot"

That's not really how I remember it. I was active on here for basically that entire time, and I can scarcely recall anyone making more than an occasional half-hearted effort to defend Bulldozer or its descendants.

The core count argument was sabotaged from the outset, because everyone knew they weren't really 8-core CPUs.

Intel's bigLITTLE is just what AMD did with Bulldozer,

That's not how I see it.

BD sacrificed Float over INT throughput and AlderLake sacrificed AVX512 over moar cores and a bit of efficiency for the whole SoC

Interesting perspective, except that the presence or absence of AVX-512 isn't fundamental to Big.Little. Intel could've theoretically added AVX-512 to the little cores and then there'd be no such compromise. In fact, that's precisely what I expect from the E-cores in Meteor Lake.

In contrast, BD's architecture fundamentally compromised floating-point. You couldn't fix that without completely changing the architecture.

 

[-Fran-]

That's not really how I remember it. I was active on here for basically that entire time, and I can scarcely recall anyone making more than an occasional half-hearted effort to defend Bulldozer or its descendants.

The main thread for the AMD rumours from way back then still exists. Go and read it. You will also read how mad I was when it released.

The core count argument was sabotaged from the outset, because everyone knew they weren't really 8-core CPUs.

In the pure sense of what the classic official definition of what a CPU is, AMD was right. From the modern concept of what a CPU contains and can do, splitting instructions on decode is a nasty trick when you have that big of a penalty. It's a pedantry thing vs what you feel is correct/right. The second one was the main argument from the Intel camp, since they didn't have to split anything when decoding and had no penalties by just relying on SMT. Vis a vis, Bulldozer did have great throughput when used correctly, but no one wanted to optimize for it, so it flopped like a Magikarp on dry soil.

Interesting perspective, except that the presence or absence of AVX-512 isn't fundamental to Big.Little. Intel could've theoretically added AVX-512 to the little cores and then there'd be no such compromise. Whereas, BD's architecture fundamentally compromised floating-point. You couldn't fix that without completely changing the architecture.

Which makes it arguably more embarrassing for Intel: it was not intended to design a full blown chip with AVX512 to have to disable it because their scheduler shenanigans did not work as they wanted. So this forced the whole line up to not support it, which is bananas. It would've been so hilarious the i5 12400 dominating the i9 12900KS in AVX512 workloads, so they definitely didn't want that. And from what I know, Raptor Lake is still a full fat P-core (including AVX512), but not enabling it. They're wasting so much space in the silicon for something they won't use it's hilarious. And this is not defects even. As you say, Bulldozer was designed that way and it worked as intended. Alder Lake was designed to work one way, but it didn't, so they had to disable AVX512. Again, AVX512 in the desktop doesn't really matter that much (if at all), but we'll see how Zen4 takes advantage of having AVX512 before Intel can work out the quirks of bigLITTLE's mixed ISA support. I don't understand why they don't want to give the little cores AVX512 support either... We had quite an interesting conversation in the Tom's Discord about what Intel could do, but it's not an easy thing to solve. There's a lot of trade offs on any way they go about it.

Regards.

 

[TerryLaze]

The issue is a very simple one, and it doesn't take so many words to understand. The E-cores are neither as fast, nor do they use as much power as P-cores. Therefore, they should not be seen as equivalent to P-cores, and you obviously don't.

Aaaaand we are back at the beginning...
When you have 16 real cores and all of them are doing heavy work, then the real cores also are neither as fast, nor do they use as much power as real cores that run alone.
6W compared to 20w and we already talked about the 30% faster in clocks.
So again, how is comparing e-cores to real cores different or wrong when you are talking about a large number of cores?!

And I only show the AMD numbers because they are easy to find, if anybody has a similar graph with a 16 core intel cpu I'm gonna be showing that.

 

[TerryLaze]

Funny how in the Bulldozer times peple was like "but IPC is king! number of cores is moot" when AMD claimed 8 "proper" cores (which it wasn't, in all honesty). Intel's bigLITTLE is just what AMD did with Bulldozer, but better: BD sacrificed Float over INT throughput and AlderLake sacrificed AVX512 over moar cores and a bit of efficiency for the whole SoC (increasing through put, like BD wanted to do as well). That's perfectly valid as long as the trade offs are understood.

Interesting how Zen4 will take a similar approach for AVX512 as BD did back in the day. Zen5 should have full fat AVX512 support, from what I understand.

Regards.

But the whole point is that with alder you do not lose any IPC, on your 8 main cores.
So IPC is still king, you can have all the cores of the 12900 doing work and the main 8 cores are still going to run at the same speed they would without having the e-cores.

 

[bit_user]

... They're wasting so much space in the silicon for something they won't use it's hilarious. ... I don't understand why they don't want to give the little cores AVX512 support either...

You said it, yourself. Adding AVX-512 to the E-cores would've made them much significantly bigger (not to mention more power-hungry).

It'll be an easier lift on the "Intel 4" node.

We had quite an interesting conversation in the Tom's Discord about what Intel could do, but it's not an easy thing to solve. There's a lot of trade offs on any way they go about it.

OMG. There's a discord, too?

Anyway, there's no realistic chance for a hybrid-ISA CPU. You might think "oh, just trap the AVX-512 instructions and fault the thread over to a P-core", but this can quickly hamper the performance of hybrid-naive code. And it's unrealistic to expect apps to be fully hybrid-aware, due to often-opaque libraries they use.

I agree with where Intel ended up, even though I know it must've been painful.

 

[bit_user]

Aaaaand we are back at the beginning...

No, we're not. We never were here, and we're not here again.

You're not helping.

 

[-Fran-]

But the whole point is that with alder you do not lose any IPC, on your 8 main cores.
So IPC is still king, you can have all the cores of the 12900 doing work and the main 8 cores are still going to run at the same speed they would without having the e-cores.

Keep in mind what "IPC" really stands for. A uARch designed to "go fast" (Intel Pentium 4's NetBurst and Bulldozer) will inherently be lower IPC than a comparable longer-staged uArch like Intel has been using since they realized Pentium 3 was the right way all along (you can compare Core2 and you'll find a lot of Pentium 3 in it). What you care about is IPC+clocks all the time; what we should all call "performance per app". This is just being pedantic, again, but I understand the underlying implication about having "faster" cores than a lot of them to get the same amount of "stuff" (or work?) done. When putting the small cores and big cores through similar workloads, I'm sure their "IPC" is fairly similar, but their clock speed difference is monstrous. Plus they have completely different approaches on their pipelines.

This is an excellent read on the subject from the Bulldozer prespective:
https://www.anandtech.com/Show/Inde...3&slug=the-bulldozer-review-amd-fx8150-tested

Regards.

 

[-Fran-]

You said it, yourself. Adding AVX-512 to the E-cores would've made them much significantly bigger (not to mention more power-hungry).

It'll be an easier lift on the "Intel 4" node.

Not really. I mean, yes, strictly speaking, but it's always a relative answer. Adding AVX512 doesn't need to be exactly the same as with the big cores for the little ones. They will be bigger, but it's all about what is the trade-off. I'm guessing even Intel doesn't consider AVX512* that important for consumer, hence why I'm curious about how AMD will use this.

OMG. There's a discord, too?

Yes

Anyway, there's no realistic chance for a hybrid-ISA CPU. You might think "oh, just trap the AVX-512 instructions and fault the thread over to a P-core", but this can quickly hamper the performance of hybrid-naive code. And it's unrealistic to expect apps to be fully hybrid-aware, due to often-opaque libraries they use.

I agree with where Intel ended up, even though I know it must've been painful.

Basically, among a few other things, yes.

Regards.

 

[KyaraM]

Funny how in the Bulldozer times peple was like "but IPC is king! number of cores is moot" when AMD claimed 8 "proper" cores (which it wasn't, in all honesty). Intel's bigLITTLE is just what AMD did with Bulldozer, but better: BD sacrificed Float over INT throughput and AlderLake sacrificed AVX512 over moar cores and a bit of efficiency for the whole SoC (increasing through put, like BD wanted to do as well). That's perfectly valid as long as the trade offs are understood.

Interesting how Zen4 will take a similar approach for AVX512 as BD did back in the day. Zen5 should have full fat AVX512 support, from what I understand.

Regards.

The issue with Bulldozer was that they were advertized as 8 real cores, when actually they were more like 4 cores with four additional threads, just those threads were their own cores, not HT, if that makes sense. It's false advertisement to advertize them as fully functional 8-core CPUs when they aren't, as also stated in the court verdict about this. Intel doesn't advertise the e-cores as equivalent to the p-cores. That's the difference.

 

[-Fran-]

The issue with Bulldozer was that they were advertized as 8 real cores, when actually they were more like 4 cores with four additional threads, just those threads were their own cores, not HT, if that makes sense. It's false advertisement to advertize them as fully functional 8-core CPUs when they aren't, as also stated in the court verdict about this. Intel doesn't advertise the e-cores as equivalent to the p-cores. That's the difference.

Yes, I know.

This is a good read on that: https://www.anandtech.com/show/14804/amd-settlement

The formal definition (old one?) just states you can call something a CPU by having very few things: decode, INT and registers. So yeah.

EDIT: One asterisk, though: Intel does call the little cores "a full CPU unit" as they do count them as "cores" in the "this is a full fledged CPU" sense, and they're right.

Regards.

 

[KyaraM]

Yes, I know.

This is a good read on that: https://www.anandtech.com/show/14804/amd-settlement

The formal definition (old one?) just states you can call something a CPU by having very few things: decode, INT and registers. So yeah.

EDIT: One asterisk, though: Intel does call the little cores "a full CPU unit" as they do count them as "cores" in the "this is a full fledged CPU" sense, and they're right.

Regards.

By equivalent to the p-cores I wanted to say equivalent in performance. Which they aren't, and Intel doesn't claim they are. Should have stated that in my post above, my bad. Of course they are real cores, that's no question.

 

[bit_user]

When putting the small cores and big cores through similar workloads, I'm sure their "IPC" is fairly similar,

No, it's not. Gracemont only has IPC equivalent to Skylake. Golden Cove has much higher IPC than that, and it clocks higher. Both are reasons for the size disparity (not to mention the performance difference).

 

[-Fran-]

No, it's not. Gracemont only has IPC equivalent to Skylake. Golden Cove has much higher IPC than that, and it clocks higher. Both are reasons for the size disparity (not to mention the performance difference).

It's about a 40% IPC difference over a 4X die space area. That for me is "similar", specially considering that the performance difference jumps to like 100% (or more) when they clock the P-cores as high as they do when the E-cores just don't go higher than ~4.1ghz. But fair, I guess on paper with nothing else into consideration a 40% difference is not "small", so I'll concede that point. From a pure performance standpoint, the E-cores are not even Skylake level purely because of how they clock.

This is a good comparison of them:
https://www.techpowerup.com/review/intel-core-i9-12900k-e-cores-only-performance/2.html

You can see how the E-cores do perform well, but hardly "Skylake" level (pure CPU vs CPU). They only beat CPUs from that era on account they are full 8c/8t instead of 4c/8t. I always cringed when Intel said "IPC like Skylake! lookie look!" and didn't give more context for them, but that's fine. The E-cores aren't a bad thing for Intel, everything considered. They need them and that's all there is to it.

Regards.

 

[bit_user]

It's about a 40% IPC difference over a 4X die space area.

IPC is not normalized by die area. Apple and ARM's E-cores are even smaller, relative to their P-cores.

That for me is "similar",

You're pretty much alone, in that regard. None of the experts would seem to consider a 40% IPC delta "similar". There's not even big of a difference between Sandybridge and Skylake.

specially considering that the performance difference jumps to like 100% (or more) when they clock the P-cores as high as they do

None of the single-threaded benchmarks I've seen show quite such a drastic discrepancy. It's only when you compare the 8 E-cores to the 8 P-cores (with 2-threads each), where such dramatic difference emerge. In this case, the differences are likely exacerbated by system-level factors (e.g. each quad sharing L2 cache and ring bus interface).

 

[InvalidError]

They're wasting so much space in the silicon for something they won't use it's hilarious.

Intel uses the same die for mainstream desktop and entry-level workstation/server. The Xeon E-33xx lineup will likely have AVX512 whenever it launches.

 

[-Fran-]

Intel uses the same die for mainstream desktop and entry-level workstation/server. The Xeon E-33xx lineup will likely have AVX512 whenever it launches.

That is true, I guess. Will they use special Xeon variants with more than 8 P-cores with monolithic dies, though?

Regards.

 

[InvalidError]

That is true, I guess. Will they use special Xeon variants with more than 8 P-cores with monolithic dies, though?

AFAIK, the low-end Xeons based on desktop dies have always used exactly the same dies. The only thing that changes is the complement of locked/unlocked features: servers get ECC and a couple of other server-centric features enabled, overclocking and a few other mainstream-oriented features disabled, dongle-locked to workstation/server chipsets so they cannot be used on mainstream boards featuring the same socket.

 

[bit_user]

Intel uses the same die for mainstream desktop and entry-level workstation/server. The Xeon E-33xx lineup will likely have AVX512 whenever it launches.

Skylake Xeon E did not have AVX-512 - only the Xeon W 2000- and 3000- series, which are actually different dies than mainstream desktop.

As for Alder Lake Xeon E, I doubt there will be such a thing. Intel officially supports ECC with regular Alder Lake CPU models, as long as you're using it in a W680-chipset motherboard. To me, that says they're not going to bother with a separate Xeon E line, at least this time around. Also, you'd have expected them to launch it by now, if they were going to. The Xeon E-series usually lag the mainstream desktop version by a few months, but they've never been so late with it.

Now, who can say whether the lack of a Xeon E is an answer to Ryzen's support for ECC, or just as a matter of expediency?

 

[bit_user]

That is true, I guess. Will they use special Xeon variants with more than 8 P-cores with monolithic dies, though?

Yes. They have published roadmaps with Sapphire Rapids-based Xeon W CPUs. Those will be P-only and will have AVX-512, as well as probably AMX and perhaps DSA (Data Streaming Accelerator). Maybe even CXL 1.1.

So, the E-core haters will have options for getting more P-cores, ...if they're willing to pay for it!

 

[InvalidError]

Skylake Xeon E did not have AVX-512 - only the Xeon W 2000- and 3000- series, which are actually different dies than mainstream desktop.

No surprise that the Xeon E and W use different dies since E is the entry-level chip based on mainstream chips and socket while W is the "HEDT" trim with no IGP, quad channels and extra PCIe. My comment was in the context of strictly LGA1xxx platforms, the lowest-end server segment and those Xeons use the same dies.

Alder Lake S does have AVX-512 available though locked out post-launch by firmware that Intel could decide to enable in the Xeon E series if it feels like it.