If you're asking about the difference in write amplification, that is write amplification factor as the ratio between NAND and host writes, for SATA drives it would not be uncommon to see DRAM-less drives having twice the wear rate of DRAM drives, e.g. 3.0 vs. 1.5 WAF. It depends on the workload and drive characteristics, although these numbers are very low with the understanding that consumer workloads are read-heavy with lots of idle time, although random writes are not untypical for OS usage. I say drive characteristics because even something as "simple" as erase block size (e.g. larger with QLC) can impact WAF greatly, for example quadrupling pages per block could double or triple WAF with concern to garbage collection. I have documentation to back this up as I covered it on my discord server recently. As for NVMe drives, yes HMB is a good option, but it has far higher access latency than on-PCB DRAM (I also have a patent with SPECIFIC timings on this that I've shared on my discord) which can reduce efficiency particularly with a fuller drive. In the grand scheme of things I don't think halving endurance is even serious within the typical 3-year DRAM-less warranty period, though.
Actual flash endurance is based on many factors but if we're looking at the raw flash it largely comes down to architecture, assuming similar yield goals. As such we have a reasonable idea on guaranteed endurance as it's on the datasheet, e.g. Micron's 96L B27B is 3000 PEC, including in SLC mode, e.g. 30K/40K PEC depending. You'll note that Micron's 96L B27A is rated for a lower PEC than B27B. This is due to geometric differences, for example the block size is much smaller on B27B; reference my point above about this, keeping in mind the influence of DRAM on GC (since you are migrating lots of pages from multiple blocks). In any case, you would see 1500/3000 for BiCS for example, and Samsung's older 3D TLC is rated for 10K+ PEC (but it's difficult to find these datasheets), although actual endurance will be higher still. Generally I would expect 3K PEC from 3D TLC as a guarantee with 5-10K PEC being a realistic result and up to 20K PEC for the best replacement gate TLC, keeping in mind Micron's 128L TLC was rated for 5000 PEC.
That being said, again, PEC here would refer to NAND writes or indirectly the average block erase count (which factors into WA/WAF, but we're assuming ideal wear-leveling). However even this simple example is incomplete as you have good blocks and bad blocks due to the uneven etching aspect ratio (pillars are conical not cylindrical) plus other things like HCI (hence dummy WLs). That is to say we can dismiss host writes but cannot treat all word lines as equal, either. But further, consumer drives rely on SLC caching which impacts endurance as static SLC uses a separate wear zone (but the best blocks of each die) while dynamic uses the same as native flash and thus has additive wear potential (and lower relative endurance as it rotates through all native flash based on wear data). Thus testing endurance properly is complicated. But as you can see with the one Chia drive, 10K PEC with TLC and dynamic SLC caching is achievable (using FortisMax vs FortisFlash).