News Samsung outlines plans for 3D DRAM, which will come in the second half of the decade

[Admin]

Samsung envisions vertical channel transistor, stacked DRAMs in the next 10 years.

Samsung outlines plans for 3D DRAM, which will come in the second half of the decade : Read more

 

[usertests]

I hope someone gets there faster. For example, NEO Semiconductor:
https://www.tomshardware.com/news/3d-x-dram-roadmap-1tb-die-density-by-2030

 

[Notton]

What kind of technology are they using for sub-10nm?
I distinctly remember there being a breakthrough with a new high-K material that allows 12nm capacitors, or something to that tune.
However, I don't think I've heard news of a breakthrough allowing sub-10nm capacitors.

 

[bit_user]

I find the title's use of the term "stacked DRAM" to be somewhat misleading. It's too easily confused with die-stacking, which already exists in the form of HBM and high-density DDR4 and DDR5 packages.

Clearly, the article is talking about cell-stacking, akin to what NAND memory makers have been doing in their 3D NAND dies.

 

[gg83]

From that one slide shared, it appears sub 10nm seems not easily obtainable with current tech. And the nm size refers to the capacitor size?

 

[Max The Dragon]

Well, 3D dram, will make 128 GB+ consumer dimms possible?
It will definitely lower the price of dram in future, as 3D technology made Nand so affordable and reliable.
Plus it can give more potential to make dimms more compact without performance penalty.

 

[Notton]

From that one slide shared, it appears sub 10nm seems not easily obtainable with current tech. And the nm size refers to the capacitor size?

Yeah, DRAM is limited by the capacitor and its dielectric material.
The capacitor has to retain a charge to work, and won't hold a charge if shrunk too much.
Currently it's in the 14~12nm range.

If a better dielectric material can be made, then the capacitor can be shrunk.
AFAIK, Micron 1-gamma is a 10nm-class, but that's not supposed to arrive until 2025.

 

[Max The Dragon]

I find the title's use of the term "stacked DRAM" to be somewhat misleading. It's too easily confused with die-stacking, which already exists in the form of HBM and high density DDR4 and DDR5 packages.

Clearly, the article is talking about cell-stacking, akin to what NAND memory makers have been doing in their 3D NAND dies.

HBM is not a true "Stacking", and have nothing similar to true 3D, scince planar (2D) chips are just soldered on top of each others and those memory is highly unreliable (nearly all Radeon Vega 56 and 64 are dead now).
High density DDR packages are still planar memory. And so its still share similar technology as pre 3D Nand.

 

[bit_user]

HBM ... is highly unreliable (nearly all Radeon Vega 56 and 64 are dead now).

I can't comment on Vega 56/64 (though I have my doubts), but HBM is now used lots of server-grade products that are warrantied for probably 3-5 years of 24/7 usage. So, I call "BS" on the claim that HBM is fundamentally unreliable. If your statement about those Vegas is even true, you're just extrapolating from a single data point.

High density DDR packages are still planar memory. And so its still share similar technology as pre 3D Nand.

Without getting into a quagmire about terminology, die-stacking in server DIMMs has absolutely been a "thing" since DDR4:

https://www.anandtech.com/show/14341/samsung-samples-32-gb-ddr4-memory-chips
​

 

[usertests]

Well, 3D dram, will make 128 GB+ consumer dimms possible?
It will definitely lower the price of dram in future, as 3D technology made Nand so affordable and reliable.
Plus it can give more potential to make dimms more compact without performance penalty.

A Memorable Samsung Event - Semiwiki

Samsung hosted its first-ever Samsung Tech Week Oct 3-5 with some insightful keynotes and great food. The week led off with Samsung Foundry Forum and a keynote from Foundry president, Si-Young Choi. Attendees at Samsung Foundry’s SAFE Forum were welcomed by Ryan Lee, head of the business’ Design...

semiwiki.com

We are at 24 Gb DRAM dies right now, enabling 48 GB consumer DIMMs. 32 Gb will follow shortly, enabling 64 GB DIMMs. Motherboards are already adding support for it in advance of launch, CPU pages show 256 GB support (4 DIMMs), etc.

The Samsung roadmap above shows 48 Gb after a 4 year gap, not using 3D technology. So that gets us to the 96 GB DIMM.

3D DRAM should not only make 128 GB+ possible, it should make 1 TB+ possible. Cost per bit might not decrease as fast as capacity can increase, but we can accept that.

 

[bit_user]

3D DRAM should not only make 128 GB+ possible, it should make 1 TB+ possible.

Yeah, I recall recently seeing someone talking about 1 TB DIMMs. Found it:

https://www.tomshardware.com/news/micron-preps-32gb-ddr5-chips-opening-doors-to-1tb-modules
​

 

[usertests]

Yeah, I recall recently seeing someone talking about 1 TB DIMMs. Found it:

​

https://www.tomshardware.com/news/micron-preps-32gb-ddr5-chips-opening-doors-to-1tb-modules​

​

Any die stacking using TSVs could presumably be combined with 3D DRAM, so you could talk 1 TB DIMMs for consumers (eventually, not immediately after introduction), and 16 TB DIMMs for enterprise or whatever the gulf between the two segments will be. They can fit more chips on, do double height DIMMs, or probably start rejecting DIMMs in favor of PCIe/CXL cards.

 

[Max The Dragon]

I can't comment on Vega 56/64 (though I have my doubts), but HBM is now used lots of server-grade products that are warrantied for probably 3-5 years of 24/7 usage. So, I call "BS" on the claim that HBM is fundamentally unreliable. If your statement about those Vegas is even true, you're just extrapolating from a single data point.

Well i talking about consumer market here, the Vega 56/64 is an single HBM based cards on market for years (if we don`t talk about Radeon R9 Fury X), and they are all mostly dead because of dead memory that you can`t replace, and yes, ability to repair is the point too.
Consumer grade hardware is different than server grade, the server grade hardware need to have extreme levels of reliable, but in a cost of BIG prices.

Without getting into a quagmire about terminology, die-stacking in server DIMMs has absolutely been a "thing" since DDR4:

https://www.anandtech.com/show/14341/samsung-samples-32-gb-ddr4-memory-chips

Die stacking as in HBM is not an 3D and maybe you are wrong here.
I think that they do that "memory stack (or die-stacking, as you say)" trick like that, by placing two dram crystal near each other in single package, because dram crystals itself are way smaller than the package. This method is used by all brands for GDDR6 and GDDR6X to double the chip capacity, but i cant find photo of sanded DRAM chip that shows it:

 

[bit_user]

Die stacking as in HBM is not an 3D and maybe you are wrong here.
I think that they do that "memory stack (or die-stacking, as you say)" trick like that, by placing two dram crystal near each other in single package,

Nope. HBM uses TSV's (through-silicon vias) to extend connectivity through the stack.

"High Bandwidth Memory (HBM) is a computer memory interface for 3D-stacked synchronous dynamic random-access memory (SDRAM) ..."

Source: https://en.wikipedia.org/wiki/High_Bandwidth_Memory

See the HBM stack in the upper-right.
​

Even in DDR4 modules, this proves 3D stacking is a real thing:

"The 16Gb, 2-high (2H) and 32Gb, 4-high (4H) 3-dimensional stack (3DS) DDR4 SDRAM use Micron’s special 3DS 8Gb DDR4 SDRAM organized as two or four logical ranks."

https://media-www.micron.com/-/medi...32gb_x4_x8_3ds_ddr4_sdram.pdf?rev=77c8db7a371
​

Do you ever fact-check any of this stuff? You should try it! Also, maybe take a minute and proof-read your posts.

 

[Max The Dragon]

Even in DDR4 modules, this proves 3D stacking is a real thing:

"The 16Gb, 2-high (2H) and 32Gb, 4-high (4H) 3-dimensional stack (3DS) DDR4 SDRAM use Micron’s special 3DS 8Gb DDR4 SDRAM organized as two or four logical ranks."

Well its just a copy of HBM planar die stacking, but interpolated to traditional dram. And this "3D" stack definitely will give performance penalty. Because its a still, MULTIPLE DIE`S stacked on each other. And I ain't see that 3ds memory on consumer market, only some examples on server market.
And it's still ain't real 3D, where the single die have multiple layers as on 3D Nand.

Do you ever fact-check any of this stuff? You should try it! Also, maybe take a minute and proof-read your posts.

Don`t be so mean, i know about that, but its still NOT a TRUE 3D.
And this is my main point here, stacked 2D die`s are NOT 3D.

 

[subspruce]

Well its just a copy of HBM planar die stacking, but interpolated to traditional dram. And this "3D" stack definitely will give performance penalty. Because its a still, MULTIPLE DIE`S stacked on each other. And I ain't see that 3ds memory on consumer market, only some examples on server market.
And it's still ain't real 3D, where the single die have multiple layers as on 3D Nand.

Don`t be so mean, i know about that, but its still NOT a TRUE 3D.
And this is my main point here, stacked 2D die`s are NOT 3D.

that's like saying a stack of paper is flat, each sheet of paper looks flat, but has a small amount of thickness, making the thickness proportional to the amount of sheets. Ever seen a book? That's a glorified stack of paper with stuff printed on it