5nm isn't publically available yet, but Samsung is already making big steps in the 3nm space.
Samsung Prototypes First Ever 3nm GAAFET Semiconductor : Read more
Samsung Prototypes First Ever 3nm GAAFET Semiconductor : Read more
Out of curiosity, how are these tech companies getting past the 7nm barrier? Several years back, when we were anxiously awaiting the 14nm technology, I remember reading that science would hit a wall at 7nm due to that mathematically being the smallest reachable size without melting the transistor, unless a new material was found to replace silicone. Now I don't claim to understand that, but I do remember reading it.
Between then and now, what happened that allowed them to break that barrier?
That should not be too much of a concern, as the worst case hit I have read for 3-5nm is 20%, which they should be able to erase through normal process node optimization and (for CPUs) IPC improvements with the more advanced architectures enabled by the increased density.... The only thing I haven't seen much about is the frequencies which is what concerns me the most.
I mean that's already happened... 5 TFLOPs is pretty decent. If you strictly mean standard consumer APUs, they'll improve, but so will dGPUs. Developers will in turn seek to harness varying degrees of this extra horsepower. So it's hard to predict if they'll get much further than the current esports / less demanding games / older games capability. I think a lot of that depends on how aggressive Intel gets with their iGPUs, as competition will be crucial to more rapid improvements on the graphics side of APUs.The densities are going to be insane. Having APU's that can really play games is going to be possible.
Not long. I just bumped into an apparent CPU architectural improvement recently regarding the performance of the load effective address instruction on x86/x64. Apparently the latency of the compound adder was reduced and compilers have already been rewritten to take it advantage of it in general purpose summing for better pipeline parallelization of normal code. The combination of hardware and software optimization should prevent the release of any new architectures where an IPC regression would actually occur... but we may have to get used to no more than 5% IPC improvement per generation below 7 mm.It may be overcome quickly but I have some doubts on how long it will take.
Out of curiosity, how are these tech companies getting past the 7nm barrier? Several years back, when we were anxiously awaiting the 14nm technology, I remember reading that science would hit a wall at 7nm due to that mathematically being the smallest reachable size without melting the transistor, unless a new material was found to replace silicone. Now I don't claim to understand that, but I do remember reading it.
Between then and now, what happened that allowed them to break that barrier?