Samsung Reveals 4nm Process Generation, Full Foundry Roadmap

[InvalidError]

That's some pretty cheap electricity! At $0.11/kWh, it's cheaper than my residential rate. And that's not even including cooling. Where did you get those numbers?

Canada has two provinces (Manitoba and Quebec) with power costs around $0.08/kWh. As a bonus, companies that build datacenters over there can get most of their cooling done by simply "opening the windows" through most of the year.

 

[bit_user]

I pay At $0.09/kWh that's in Texas. Albeit I signed a 3 year contract when it had dipped low.

I pay north of $0.20/kWh, when you factor in generation + delivery charges. And the commercial rate is more than 3x that much!

Plus, my math was simply converting his $500/year cost estimate to $/kWh. There's still cooling to be accounted for.

 

[waynes]

What ever, happened to 7nm being the point where leakage caused decreased size past that to offer no energy savings, but only increased energy per clock increase, with 5nm being the functional limit (according to a nvidia article years back)?

 

[Karadjgne]

Advances in technology have changed node design, alloys, manufacturing etc, so what was thought of as true back when nvidia released that, was only true for its current time frame. Wasn't that long ago when 23nm was the big thing and consideration to go as small as 7nm was a physically impossible dream.

 

[InvalidError]

Wasn't that long ago when 23nm was the big thing and consideration to go as small as 7nm was a physically impossible dream.

The industry always knew that it would eventually go beyond 22nm, it merely turned out more difficult than expected. In the case of 7nm and beyond though, we're getting close to the theoretical limits of what is physically possible using silicon as the base material. When electrons can tunnel straight through the insulation between traces/layers and quantum effects dominate how transistors operate even when they aren't meant to, most traditional semiconductor design, manufacturing and materials go out the window. At the moment, the industry still hasn't found cost-effective materials and processes to replace silicon. Many potentially promising leads, all with at least one major shortcoming.

 

[waynes]

Thanks Karadjgne and Invaliderror. But how are they going to use silicon to go below 4nm now? Also, do you have a link to that nvidia article, I couldn't find it again?

 

[InvalidError]

But how are they going to use silicon to go below 4nm now?

They can't.

Below 4nm, electrons can spontaneously jump through silicon by quantum tunneling even when there are no defects or contaminants in the silicon oxide insulation, which makes it impossible to use silicon as insulation between traces and layers. To go beyond 4nm, new materials and material combinations capable of inhibiting quantum tunneling at tighter conductor spacing are required.

 

[waynes]

Sorry I should have said below 7nm instead. But where do power savings stop now, as they seem to indicate it has moved below 7nm?

Maybe the problem is use of electrons. Can magnetic fields go lower?

What is the bond distance between atoms on a chip?

 

[waynes]

Well thanks anyway for the advice.

 

[Karadjgne]

The other half of the problem isn't just the insulation factor vrs quantum tunneling, but manufacturing process, carbon would be decent or any other atom that's electron full in its outer ring, but actually getting it formed the way silicon can be molded is going to be a problem. There's also the issue of bleed, the smaller the nm process, the greater chances of bleed at OC levels, the shorter the lifespan of the cpu, the lower the OC limits. It would stand to reason that if you stuck a 7nm process node, with the same transistor count on a 14nm die, effectively doubling the insulation factor, you'd be able to get higher speed cpus without the backlash of bleed or tunneling.

 

[JamesSneed]

Advances in technology have changed node design, alloys, manufacturing etc, so what was thought of as true back when nvidia released that, was only true for its current time frame. Wasn't that long ago when 23nm was the big thing and consideration to go as small as 7nm was a physically impossible dream.

I'm a bit skeptical as well. They are using a "Nanosheet" to help overcome this but the details are a bit light.

 

[InvalidError]

There's also the issue of bleed, the smaller the nm process, the greater chances of bleed at OC levels, the shorter the lifespan of the cpu, the lower the OC limits.

If by 'bleed' you mean electrical leakage or electromigration, both are technically still issues even at stock speeds. Many tweaks have been applied to silicon chip design and manufacturing processes to mitigate both but below 14nm, there isn't much room left to fit passivation layers and new work-arounds may be necessary.

When quantum tunneling passes electrical leakage as the primary contributor to static power draw, it'll be nearly impossible to go any further.

BTW, it isn't process that is limiting OC, it is architecture - the tradeoff between doing more work per clock by giving the circuitry more time to settle between time steps vs reaching higher clocks by cutting things down into smaller steps. As Intel has demonstrated with Netburst and AMD proved with FX, sacrificing work per clock in the pursuit of high clock speeds is ultimately counter-productive: it yields under-performing power-guzzling architectures.

 

[Karadjgne]

I was thinking more of power than clock speeds. The more current/voltage applied through the process, the greater the chance of bleed or tunneling, the higher the necessity of insulation. If you can mitigate the damage done by electromigration or tunneling, you could push higher power levels. By the time you get down to 7nm, there's nothing left no room for error or tweaks, as you say. It'd be like having a cpu that's stable at 2.0v instead of 1.4v without the use of LN2