[citation][nom]Filiprino[/nom]19 nm. We're getting really small. Wasn't today's limit 11 nm?[/citation]
Technically it's around 6nm before quantum tunnelling becomes a significant problem. At least for CPUs. Storage is more resistant to random failures as it usually has error correction built in so maybe a fair amount of random data changes is acceptable with the right controller technology, so for flash RAM cells the limit may be stretched to 4nm.
It will also depend on manufacturing process technology, and let's not forget that there's a tendency to cells having more than just one or two bits per cell. Already we have 3 bits per cell and future implementations will likely see 4, 5 or even 8 bits per cell.