ARM is a RISC, not so long ago ARM = Accorn RISC Machine, but now it (patented) just ARM.other than being open source, what are the benefits of RISC vs x86/ARM/etc...
what type of workload would be considered simple vs complex? the article speaks of AVX type loads being added. wonder what else would be considered complex vs simple calculations.ARM is a RISC, not so long ago ARM = Accorn RISC Machine, but now it (patented) just ARM.
Now in the topic of RISC vs CISC, the R in RISC stands for Reduced (as opposite Complex in the CISC), meaning that the number of instruction that can be executed (called Instruction Set) of RISC are significanly lower compare to the CISC, and the instruction on the RISC is (usually) fixed length compare to variable length in CISC, this translate to significantly more simple to create circuitry (in term of number of transistor budget) to execute that Instruction Set, which result fewer trace, fewer power needed, more efficient, etc.
The chip needed to run RISC is significantly smaller (in term transistor budget) than CISC, and needed far less power to operate. The catch is, because number of Instruction is limited, to perform complex calculation it has to do more step (cycle) than the CISC. For example, if for particular computation the CISC only need 3 cycle, the same computation maybe need 15-25 cycle in RISC, because the RISC need to emulate that complex computation into several simple computation.
In general, if the load is 70:30 (simple:complex) computation, the the RISC machine with same clock speed is 30% slower than CISC machine, but need much less power to operate, this is why the RISC is widely adopted in portable/mobile device and devices that do not need complex computation. This of course is in assumption that everything else is being equal, no optimization, no specificc circuit, etc.
Careful - RISC and RISC-V are very different things.other than being open source, what are the benefits of RISC vs x86/ARM/etc...
Cray did vector instruction in 1976 -- https://www.hpcwire.com/2016/09/26/vectors-old-became-new-supercomputing/
I think you've got that backwards. The R in RISC is for "Reduced", while the "C" in CISC is for "Complex".Typically a single RISC instruction consists of several simple sub-instructions (micro operations) that the CPU core can execute directly. The efficiency of RISC is that one single "instruction" can do multiple integer and arithmetic operations together. That is why RISC can execute more operations than CISC per single instruction cycle or per clock cycle... 🤠
On the other hand, a single CISC instruction will be need to be translated into sub-instructions (micro operations) that can be executed within the CPU core. Usually one CISC instruction can only do a single integer or arithmethic operation.
Here are some benchmarks from their earlier generation, compared with the ARM-based Nvidia Tegra TX2. It's not pretty, but I think the point was more to have a functional software development platform than a performance-competitive core:Yet to see any performance figures from these new (alternative) CPUs.
Performance will take a while, and needs someone with extremely deep pockets to invest BIG in a high-performance core. Just look at how long it's taken ARM to reach a compititive stance vs. x86!Can they even compete with the current crop of CPUs, in terms of performance (to be useable)?
Right now, Linux seems well-supported. And with Linux support, you can build most open source software for it. So, for embedded applications and certain cloud uses, it could be reaching viability.Another issue is development and software ecosystem.
that makes sense. a new way of looking at chip design vs band-aid updates to keep an old platform current. never thought of it that way. but like ipv4 vs 6 even newer, better optimized and designed for modern uses is not enough most of the time to get us to move forward. too much invested in the old tech to move happily. it would take a good leap in performance past x86 to get us to move from it for sure. that much i know is true.The main advantage of RISC-V is simply that it's newer and better-matched to current semiconductor manufacturing capabilities and toolchains. x86 is a creature its day, and keeps getting pumped up botox and plastic surgery to appear fun an exciting, but at a phenomenal cost in terms of engineering resources and power-efficiency. In the end, it's fighting a losing battle.
Well, perhaps you've heard that Apple is ditching x86 for their own ARM designs? ARM is another RISC-like CPU instruction set architecture (ISA). So, it's very possible.it would take a good leap in performance past x86 to get us to move from it for sure. that much i know is true.
That is incorrect, RISC not related register-to-register operations as it can also be done with CISC as well (with MOVs). Address generation in CISC is also automatically handled..I think you've got that backwards. The R in RISC is for "Reduced", while the "C" in CISC is for "Complex".
A typical example would be how a CISC instruction can combine the instruction's core function (let's say dividing one number by another) with address arithmetic and a load and/or store, in case a source or destination was in memory instead of a register.
Classical RISC instructions would operate register-to-register. If you wanted a load or store, that was a separate instruction. And if you needed to do any address arithmetic (such as adding a constant offset), that would be another instruction - just a normal addition instruction. The idea was that by making the instructions simpler, they could be implemented more efficiently and you saved silicon budget for optimizations like pipelining or superscalar execution. They would also tend to clock higher. The theory was that the net effect would be higher throughput, in spite of the need to execute more instructions to do the same work.
Funny thing is that they implemented an ARM chip, which relies on patents and standards set by ARM. With Nvidia now owning ARM, Apple is forced to deal with Nvidia - a supplier they'd long-ago banned from their products.i recall reading about apple dumping x86 but figured it was mostly a desire to keep all tech in house if possible to avoid anyone else being able to mess with their ability to function.
I never said CISC CPU couldn't use all-register operands, just that RISC CPU would (for instance) have that restriction.That is incorrect, RISC not related register-to-register operations as it can also be done with CISC as well (with MOVs).
The RISC designs, on the other hand, included only a single flavour of any particular instruction, the ADD, for instance, would always use registers for all operands.
Can you cite any references on that? Again, it sounds like your mixing up CISC and RISC, with a dash of VLIW thrown in there. VLIW is the one where they pack multiple instructions together.The actual reason its "Reduced" is because those sub-instructions (micro operations) are only few bits wide (meaning it can be as little as 8 to 16 primitive instructions just adequate for internal CPU execution) within the main instruction body itself. RISC can have use this very small set of sub-instructions (micro operations) in various combinations to generate a single CISC-like operation or to generate multiple operations (as mentioned).
Have you seen how RISC instructions look like in bits? In most RISC implementations, a single instruction have group of bits (that "few bits wide") with each group of bits sub-intructions assigned to certain micro operations within the CPU core execution unit itself. This the very minimal number of instructions per group is how the term "reduced" came about. These sub-instructions are executed directly in the CPU core (no translation). This was the original design and structure of RISC.Can you cite any references on that? Again, it sounds like your mixing up CISC and RISC, with a dash of VLIW thrown in there. VLIW is the one where they pack multiple instructions together.
Because each set of sub-instructions is assigned to a micro operation directly within the CPU execution unit. Depending on the design of the RISC CPU core architecture (especially the super wide ones with multiple ALUs), multiple sub-instructions allows several micro operations to executed simultaneously within either a CPU execution cycle or one clock cycle. This is why RISC is highly efficient per clock or per CPU execution cycle. Although that is not always the case, still depends on the possible combination of those sub-instuctions and whether there are dependancies (some cannot be executed in the same cycle but require the next one).Firstly there is no such thing as CISC, there is RISC and not-RISC, or specifically designs that follow the RISC philosophy and design's that don't. The RISC design philosophy is simply that all instructions are the exact same size and take exactly one cycle to execute. Those two concepts, when taken together, enable much simpler pipeline and scheduling. Now not everyone followed those requirements exactly, but the idea is generally followed by every design these days.
Already mentioned this earlierAbout x86, there hasn't been a pure x86 CPU designed in decades now. Intel and AMD CPU's are internally RISC CPU's that use an instruction decoder to convert x86 instructions into Load/Store RISC instructions, schedule those instructions on internal ALU/AGU/MMU units, then return the result to the CPU stack for the next instruction to use. Intel's current uArch has 4 ALU's per code along with a bunch of other special purpose units.
On the other hand, usually CISC have more instructions ranging from 8-bit wide (256 instuctions) to 32-bit wide (up to 4 billion instructions). Hence "Complex" as the whole large instruction set can consist of highly complex CPU instructions (include memory block operations, SIMD, vector, etc) . And each of these CISC instruction will be translated into RISC-like micro-operations internally within the CPU core.
Depending on RISC implementation, memory operations can be excuted within a single RISC instruction (using multiple sub-instructions within the instruction itself). As already mentioned earlier..In the RISC world an execution instruction can only go register to register, we need to load (read) our values into the register from memory and store (write) the output back to memory. x86 on the other hand allows memory address's to be used as a source for many instructions, requiring several cycles to execute the instruction.
And also..The actual reason its "Reduced" is because those sub-instructions (micro operations) are only few bits wide (meaning it can be as little as 8 to 16 primitive instructions just adequate for internal CPU execution) within the main instruction body itself. RISC can have use this very small set of sub-instructions (micro operations) in various combinations to generate a single CISC-like operation or to generate multiple operations (as mentioned).
This means a simple memory operation with one single CISC instruction will use several sub-instructions within a single RISC instruction, just for example...