Silicon Motion SM2256 Preview

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In my review of Samsung's SM951, I talked about a new divide coming for client SSDs. PCIe-based products will make up a majority of the performance SSD segment, and a second-tier PCIe segment will touch the mainstream market. That's where we look today.

Silicon Motion SM2256 Preview : Read more
 

InvalidError

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It most likely will. Simply going from 20-22nm TLC to 14-16nm will likely ensure that with smaller trapped charge, increased leakage, more exotic dielectric materials to keep the first two in check.
 

unityole

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this is the way where we are heading, only thing to get good grade SSD is probably to spend big. good grade as in HET MLC flash and pcie 3.0 performance.
 

alextheblue

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As long as they don't corrupt data, I'm not really freaking out over endurance. When a HDD died, that was a major concern. If an SSD that's a few years old starts to really reach the end of its useful life, as long as I can recover everything and dump it onto a new drive, I'm happy.

If you have a really heavy workload though, by all means get a high-end unit.
 

jasonkaler

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Here's an idea:
While they're making 3d nand, why don't they add an extra layer for parity and then use the raid-5 algorithm?
e.g. 8 layers for data, adding 1 extra for parity. Not that much extra overhead, but data will be much more reliable.
 

InvalidError

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SSD/MMC controllers already use FAR more complex and rugged algorithms than plain parity. Parity only lets you detect single-bit errors. It only allows you to "correct" errors if you know where the error was, such as a drive failure in a RAID3/5 array. If you want to correct arbitrary errors without knowing their location beforehand, you need block codes and those require about twice as many extra bits as the number of correctable bit-errors you want to implement. (I say "about twice as many" because twice is the general requirement for uncorrelated, non-deterministic errors. If typical failures on a given media tend to be correlated or deterministic, then it becomes possible to use less than two coding bits per correctable error.)
 

jasonkaler

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No you don't. Each sector has CRC right?
So if the sector read fails CRC, simply calculate CRC replacing each layer in turn with the raid parity bit.
All of them will be off except for one with the faulty bit.
And these CRC's can all be calculated in parallel so there would be 0 overhead with regard to time.
Easy huh?
 

InvalidError

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If you know which drive/sector is bad thanks to a read error, your scheme is needlessly complicated: you can simply ignore ("erase") the known-bad data and calculate it by simply XORing all remaining volumes. But you needed the extra bits from the HDD's "CRC" to know that the sector was bad in the first place.

In the case of a silent error though, which is what you get if you have an even-count bit error when using parity alone, you have no idea where the error is or even that there ever was an error in the first place. That's why more complex error detection and correction block codes exist and are used wherever read/receive errors carry a high cost, such as performance, reliability, monetary cost or loss of data.
 

Eggz

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I know this article was about the SM2256, but the graphs really made the SanDisk PRO shine bright! In the latency tests, which content creators care about, nothing seemed to phase it, doing better than even the 850 Pro - consistently!

BUT, one significant critique I have was the density limitation. Everything here was based on the ~250 GB drives. Comparing a drive with the exact name, but in a different density, is akin to comparing two entirely different drives.

I realize producing the data can be time consuming, but having the same information at three density points would be extremely helpful for purchasing decisions - lowest, highest, and middle densities.
 

jasonkaler

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The parity bit is there for recovering the data, not checking its integrity. CRCs at the end of each data sector are there for checking its integrity.
 
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